steve
|
41f9a84a4b
|
Handle much more complex event expressions.
|
1999-05-01 02:57:52 +00:00 |
|
steve
|
ce49708442
|
Parse OR of event expressions.
|
1999-04-29 02:16:26 +00:00 |
|
steve
|
5895d3c98d
|
Add memories to the parse and elaboration phases.
|
1999-04-19 01:59:36 +00:00 |
|
steve
|
d27f260bc1
|
Check net ranges in declarations.
|
1998-11-11 00:01:51 +00:00 |
|
steve
|
ebad845fc3
|
Add procedural while loops,
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
|
1998-11-09 18:55:33 +00:00 |
|
steve
|
b118634189
|
Handle procedural conditional, and some
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
|
1998-11-07 17:05:05 +00:00 |
|
steve
|
3fb7a053be
|
Introduce verilog to CVS.
|
1998-11-03 23:28:49 +00:00 |