11b2b1740a
Handle expression widths for EEE and NEE operators,
...
add named blocks and scope handling,
add registers declared in named blocks.
1999-06-24 04:24:18 +00:00
853ad247a1
Elaborate and supprort to vvm the forever
...
and repeat statements.
1999-06-19 21:06:16 +00:00
37b60a4c52
Clean up interface of the PWire class,
...
Properly match wire ranges.
1999-06-17 05:34:42 +00:00
fabb146342
Support case expression lists.
1999-06-15 05:38:39 +00:00
d0afc9adee
Get rid of the STL vector template.
1999-06-15 03:44:53 +00:00
740c63291a
l-value part select for procedural assignments.
1999-06-13 23:51:16 +00:00
7c2cf8b2fa
Add support for the Ternary operator,
...
Add support for repeat concatenation,
Correct some seg faults cause by elaboration
errors,
Parse the casex anc casez statements.
1999-06-10 04:03:52 +00:00
7605a7b1f0
Add parse and elaboration of non-blocking assignments,
...
Replace list<PCase::Item*> with an svector version,
Add integer support.
1999-06-06 20:45:38 +00:00
35893919e0
module parameter bind by name.
1999-05-29 02:36:17 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
b44ef063a8
Fix handling of null delay statements.
1999-05-05 03:04:46 +00:00
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
ce49708442
Parse OR of event expressions.
1999-04-29 02:16:26 +00:00
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
e2a37a8ccd
Add support for module parameters.
1999-02-21 17:01:57 +00:00
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
8bdd381cdf
Parse and elaborate the Verilog CASE statement.
1999-02-03 04:20:11 +00:00
a7ad8985ac
Carry some line info to the netlist,
...
Dump line numbers for processes.
Elaborate prints errors about port vector
width mismatch
Emit better handles null statements.
1999-02-01 00:26:48 +00:00
e097c999d5
Elaborate UDP devices,
...
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
1998-12-01 00:42:13 +00:00
91aad30e1f
Parse UDP primitives all the way to pform.
1998-11-25 02:35:53 +00:00
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
6b2fa19429
Handle while loops.
1998-11-11 03:13:04 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve