90293d8e0a
vhdlpp: VTypeArray::is_variable_length() uses ScopeBase to determine if variable has constant length.
2015-02-04 16:57:43 +01:00
6d75af86e6
vhdlpp: Added Subprogram::fix_variables() method.
2015-02-04 16:57:43 +01:00
2ecfed0baa
vhdlpp: Moved part of check_unb_vector() to fix_logic_darray().
2015-02-04 16:57:43 +01:00
c287281bbe
vhdlpp: Tries to determine if function return type is fixed size.
...
Added Subprogram::fixed_return_type() method.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
...
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
d9fea802da
Function declarations in packages
...
This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
Maciej Suminski
Cary R
Stephen Williams