Commit Graph

9541 Commits

Author SHA1 Message Date
Martin Whitaker 71c36d1289 Improve error message on assignment to an array or array slice (issue #562).
This is valid SystemVerilog, but not something we support yet.
2021-11-12 21:43:24 +00:00
Martin Whitaker 61aed6882c Fix an assertion failure when a variable name is replicated in the same list. 2021-11-11 19:02:40 +00:00
Martin Whitaker 3c23180af3 Remove unreachable code.
pform_get_or_make_wire() should always return a valid pointer. Replace the
existing unreachable code with an assertion.
2021-11-11 19:02:40 +00:00
Cary R c6ef2ba809 Fix valgrind compile to work with new using std reorg 2021-11-10 18:21:14 -08:00
Martin Whitaker dcc9b59f6d Support SV [size] dimension for module and gate instances (issue #553).
Also output a proper error message if multiple dimensions are supplied
instead of failing an assertion.
2021-11-06 00:02:38 +00:00
Martin Whitaker dbf55da0f5 Clean up indentation. 2021-11-05 21:49:51 +00:00
Martin Whitaker 0e3682a127 Remove buggy assertion.
If this assert fires, the "this" pointer we pass to it will be a
null pointer, so will cause a null pointer dereference. We've
tested it is not null earlier, so we don't need the assertion.
2021-11-04 17:07:30 +00:00
Martin Whitaker 9cc09b8513 Remove "using namespace std" from vvp header files and fix the fallout. 2021-11-04 17:02:07 +00:00
Martin Whitaker 23390c1ba3 Remove "using namespace std" from tgt-vhdl header files and fix the fallout. 2021-11-04 17:01:16 +00:00
Martin Whitaker ecbbb60fb6 Remove "using namespace std" from compiler header files and fix the fallout. 2021-11-04 16:55:03 +00:00
Martin Whitaker 19e44d79ec Revert "Reorder header file inclusion to avoid "byte" name collision."
This reverts commit 4c4b09947f.

This didn't completely fix the problem, so try a different tack.
2021-11-04 10:58:49 +00:00
Martin Whitaker 4c4b09947f Reorder header file inclusion to avoid "byte" name collision.
When using the latest mingw64 header files, rpcndr.h (which is indiretly
included by windows.h) defines a type named "byte" which collides with a
definition in cpp_type_traits.h (included indirectly by the STL). This is
only a problem if "using namespace std" is declared prior to including
windows.h.
2021-11-03 18:36:13 +00:00
Martin Whitaker 829d361b17 Fix null pointer warning from latest GCC. 2021-11-03 18:07:15 +00:00
Martin Whitaker 3dda39bce3 Handle run-time out-of-bounds access for wire real arrays (issue #556). 2021-11-03 17:50:45 +00:00
Cary R e3c2234893 Update fstapi.c to the latest from GTKWave 2021-10-26 19:41:29 -07:00
Martin Whitaker ef01dd1e81 Fix signedness of non-ANSI port declarations (issue #540).
For non-ANSI port declarations that have both a port declaration and
a corresponding variable declaration, the signed attribute may be
attached to either the port declaration or the variable declaration,
or both declarations.
2021-09-10 23:09:03 +01:00
Martin Whitaker 7ee7a48310 Check that a genvar is not shadowed when used in a generate loop construct.
This also ensures the same genvar cannot be used in two nested loops
(issue #533), because the implicit localparam with the same name
shadows the genvar declaration.
2021-08-04 14:35:38 +01:00
Martin Whitaker cefcffecda Include named events in checks for name collisions. 2021-08-04 14:14:09 +01:00
Martin Whitaker a17557575d Include typedefs in checks for name collisions.
This requires us to make a copy of the typedefs map when adding it to
a NetScope object, because the pform data is deleted before we are
finished with it.
2021-08-04 14:00:33 +01:00
Martin Whitaker 7445b424f1 Avoid name collisions when naming unnamed generate blocks.
As specified in the IEEE standard, the automatically generated name
must not conflict with any explicitly declared name (not just scope
names).
2021-08-04 12:07:52 +01:00
Martin Whitaker ceb2581368 Fix naming of unnamed generate blocks (issue #528)
The IEEE standard specifies that the numbering of generate blocks
restarts at 1 in each new scope, and that the 'else' part of an 'if'
construct is part of the same constuct, so has the same number.
2021-08-04 11:58:18 +01:00
Martin Whitaker c34167b2c0 Fix detection of directly nested generate constructs.
If a generate construct is enclosed in a begin-end pair, it can't
be directly nested (1364-2005 section 12.4.2).
2021-08-04 10:37:26 +01:00
Martin Whitaker 389e2a3a94 Use a list instead of a set for storing the potential package imports.
This eliminates some indeterminism in the error messages, which was
causing occasional failures in CI. We don't expect this list to be
very large, so the O(n) insertion time should not be a problem.
2021-07-31 18:36:18 +01:00
Martin Whitaker 83d9b5deda Rework PEIdent::test_width() to use new-style symbol_search().
This fixes issue #527.
2021-07-31 14:18:52 +01:00
Martin Whitaker e547a8355d Rework PEIdent::elaborate_expr() to use new-style symbol_search(). 2021-07-31 13:19:12 +01:00
Martin Whitaker b9863b4fde Store user-supplied path to object in symbol_search results.
(wanted by next commit)
2021-07-31 12:42:53 +01:00
Martin Whitaker 3b1b611a18 Fix evaluation of out-of-bounds bit/part-select in constant function (issue #531). 2021-07-30 20:34:47 +01:00
Martin Whitaker 061121203b Fix segfault in wildcard port connection with unnamed port (issue #530).
A module port list may contain unnamed entries, e.g.

  module dut(a,);

When performing a wildcard connection, these entries should be skipped,
as there is no name to match.
2021-07-30 17:42:16 +01:00
Cary R 6b127432da Cleanup space 2021-06-20 22:51:32 -07:00
Cary R c07a6ec8fd Correctly dump case items 2021-06-20 22:39:43 -07:00
Cary R eb5b04626d Handle elaboration tasks with a single string argument 2021-06-20 22:03:55 -07:00
Cary R 31e3155426 Fix fprintf display type 2021-06-17 22:46:24 -07:00
Cary R bb2c51a174 Update fstapi files to latest from GTKWave 2021-06-17 21:41:36 -07:00
Martin Whitaker 1f8876be1c Fix .event/or connectivity when inputs have multiple fanout (issue #508).
The old implementation connected all inputs to the same vvp_net_t port,
on the basis that we don't care about the data values or what port they
arrived on. But if one or more of the inputs fans out to multiple nets,
the chains get tangled, which either results in connections being lost
or inappropriate connections being made, depending on the order that
the inputs are linked.

This could have been fixed by using a standard wide functor. But as we
don't care about the data values, that would be unnecessary overhead.
We just need separate vvp_net_t objects to handle the input connectivity
and can keep using a single shared functor.
2021-05-18 08:36:04 +01:00
Martin Whitaker 711623f682 Remove redundant elab_and_eval_lossless(). 2021-05-16 17:31:59 +01:00
Martin Whitaker a040ddc070 Do not force lossless calculation for index expressions (issue #515)
The standard Verilog expression bit length rules must be used.
2021-05-16 17:19:13 +01:00
Miodrag Milanovic 1341dee0e6 Fix for cross compile build 2021-05-12 09:16:11 +02:00
Martin Whitaker cf0bf4d9aa Record the actual data type when a module port has an enum type.
This fixes assignment compatibility problems (issue #498).
2021-04-28 20:18:04 +01:00
Martin Whitaker a7cb93842e Fix waveform dumpers to use vpiInstance when dumping all variables. 2021-04-21 09:23:19 +01:00
Martin Whitaker d2521878d7 Add support for vpiInstance as the type code in calls to vpi_iterate().
This is needed for the waveform dumpers now that vpi_iterate(vpiModule, NULL)
has been ficed to only return modules.

This includes recognising vpiProgram and vpiInterface, although the compiler
and vvp currently incorrectly classify them as modules.
2021-04-21 09:01:50 +01:00
Martin Whitaker 7d7aa0604c Properly report errors for out-of-bounds constant indexed part selects.
(replacing assertions)

The IEEE standard either requires out-of-bounds bits to be ignored on
write, returned as 1'bx on read, or requires a compile-time error message.
The latter is easier to implement.
2021-04-20 22:58:40 +01:00
Martin Whitaker 4af830187e Support indexed part selects that index sub-arrays (issue #497) 2021-04-20 21:29:00 +01:00
Martin Whitaker 7c024d6cab Fix width calculation for bit/part selects of multi-dimensioned packed arrays.
If we have a bit/part select that is selecting one or more sub-arrays, e.g.

  wire [3:0][3:0] foo;
  assign foo[1] = 4'd1;

we need to take into account the bit width of the sub-array when calculating
the bit width of the select.
2021-04-20 21:02:04 +01:00
Martin Whitaker 3167b2ed24 Don't return packages when iterating over root modules (issue #496)
The code assumed all handles stored in vpip_root_table were modules. This
is true for traditional Verilog, but not so for SystemVerilog.

Whilst here, also add support for iterating over packages.
2021-04-18 09:47:21 +01:00
Martin Whitaker d8cb29f6e0 Fix bug in preprocessor line directive handling. 2021-03-14 10:03:08 +00:00
Martin Whitaker 9a2c43ec34 Recognise and obey `line directives in the preprocessor (issue #488)
To correctly restore the file name and line number after including a
file or expanding a macro, the preprocessor needs to be aware of the
changes introduced by `line directives. The `line directive still
needs to be passed on to the main compiler so it can track the
changes too.

To avoid duplicate error messages, the preprocessor silently ignores
invalid `line directives, relying on the main compiler to report the
errors.
2021-03-13 23:38:30 +00:00
Martin Whitaker 45db0db8b3 Check that port default values are constant expressions. 2021-03-12 23:27:19 +00:00
Martin Whitaker c7eaa06a2b Add support for module input port default values (issue #489). 2021-03-10 08:21:42 +00:00
Cary R 60a77b08d2 Add compiler and the start of vvp support for ->> 2021-02-19 23:21:51 -08:00
Cary R 753bf516d6 Update the symbol search to find class properties 2021-02-16 23:46:02 -08:00