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Author SHA1 Message Date
Lars-Peter Clausen 30b70923b5 Add regression test for variable declarations in unnamed blocks 
SystemVerilog supports variable declarations in unnamed blocks, while
Verilog does not.

Add a regression test that checks for this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2022-01-23 18:52:35 +01:00