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Author SHA1 Message Date
Lars-Peter Clausen 91579c7c79 Add regression tests for parameters without default 
SystemVerilog supports parameters without default values in parameter port
list. Add regression tests to check this feature.

Also add a regression test to check that modules without a default
parameter are not automatically picked as a toplevel module.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2022-02-13 18:21:56 +01:00