5 Commits

Author	SHA1	Message	Date
steve	8bdd381cdf	Parse and elaborate the Verilog CASE statement.	1999-02-03 04:20:11 +00:00
steve	fb439c78b9	Add the LineInfo class to carry the source file ... location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.	1999-01-25 05:45:56 +00:00
steve	6b2fa19429	Handle while loops.	1998-11-11 03:13:04 +00:00
steve	b118634189	Handle procedural conditional, and some ... of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.	1998-11-07 17:05:05 +00:00
steve	3fb7a053be	Introduce verilog to CVS.	1998-11-03 23:28:49 +00:00