While a package can not have logic defined in it. It can have
variables with initializers. These initializers currently get
ignored when converting the package to a module in the
vlog95 backend.
Make sure packages are treated the same as modules here and
that the initializers are turned into initial blocks in the
generate vlog95 code.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add support for detecting when to add a $signed() or $unsigned() to
create a self-determined context. This makes the test in the test suite
pass, but there could still be issues
Since parameters are now passed by reference use that information to print
the parameter name in a select vs trying to figure it out by searching the
scope looking for a parameter with the same file, line and value information.
Only print the $signed() may need to be removed messages for a select
expression that will actually be cast to signed.
Use the actual parameter information to warn that -pallowsigned=1 is needed
for a parameter when the LSB > MSB.
The actual signal code is trivial, but the emit expression code needed
to be enhanced to pass a flag that says if one of the arguments in a
binary (except the shifts) or ternary (excluding the condition) context
is unsigned. This information is used to prevent emitting an explicit
$unsigned() for a signal that is used in this context since it will be
implicitly cast to unsigned.
This patch finishes the code needed to translate a SystemVerilog package to a
module with a special name. It also adds code to report that class scopes are
not supported and treats both a class and package as a top level scope.
There are limitations with this since the compiler does not pass all
the information that was present in the original source, but it is enough
to get a valid simulation result. It is not enough for timing analysis!
specparams are also incorrectly translated to parameters so they show up
in the wrong place.
In SystemVerilog a task or function can initialize a variable in a task or
function. In Icarus this is done by creating an initial block that does
the assignment. We can translate this by emitting the initial block in the
enclosing module scope. This is not 100% correct since SystemVerilog
requires the initialization to be done before the other initial/always
blocks are processed. For SystemVerilog the current Icarus behavior is
incorrect, but even if it had a new process type that ran before the other
ones the best I can do for vlog95 is emit it before the normal module
processes which currently works.
We can not convert SystemVerilog strings or dynamic arrays to valid vlog95.
This patch adds an error message that they are not supported. There are still
issues with converting some of the dynamic array constructs (the compiler
crashes), but the message is printed before the crash.
This patch adds support for SystemVerilog packed arrays and adds sorry
messages for generate blocks as well as the new SV final and
fork/join_any/join_none statements.
Rework the nexus emitting code to correctly translate most I/O ports.
Fix a few other expression issues uncovered when port translation was
done correctly. Ignore and warn that the SV ++/-- operators and enum
types are not translatable. More updates of the nexus debug code.
This patch adds support for correctly handling most unconnected ports.
Most important is top level ports that are the root of the conversion.
This patch also adds support for emitting more signed constructs when
they are requested. $signed() and $unsigned() are still not supported
or recognized as an error when not emitting signed constructs.
This patch adds a flag -pallowsigned=1 to the vlog95 converter that
tells it to allow signed signals. There is currently no code to check
for and warn/emit the $signed() and $unsigned() system functions. I
need to determine if >>> emitting should also be controlled by the
allow signed flag.
This patch adds support for emitting escaped identifiers and adds
code to correctly emit most module port expressions/definitions.
There are some minor code optimizations/cleanup included as well.
This patch adds support for emitting fixed CA selects (zero based
variable bit and array selects also work), emitting a for statement
as a single statement and fixes for numerous little bugs. It also
adds the start of emitting module port information.
This patch adds a flag that emits file and line information for
most lines. This can help the user understand where the various
lines came from in the original code. They are printed as
comments so the generated code still runs correctly.
This patch adds the following to the vlog95 converter.
Add support for emitting and calling UDPs.
Generate a UDP for a synthesized DFF.
Add the ability do emit a constant assigned to a net.
This patch moves the logic and lpm code to a new file. It refactors
the strength emitting routine and adds support for emitting the
standard tran style of gates.
This patch adds the ability to translate the code produced by the
compiler for a wait statement back into a wait statement. It also
reworks the strength emitting code to only emit a single strength
for the pull gates and fixes a bug in the strength emitting code.
This patch add the following functionality to the vlog95 generator.
Add support for most CAs. Selects still don't work correctly.
Emitting a named event as an expression.
Enhance the ability to find a signal in a nexus.
Add code to emit a nexus driven by a constant.
Rework the delay/strength code for logic gates/CAs
Refactor some of the number code.
Refactor the variable emitting code to support named blocks.
Translate the compiler code back to <var> = <event> <value>
This patch adds support for emitting an array as an expression. This is
used as a system task/function argument.
It partially reworks the real display code to print an appropriate
expression for NaN, inf and -inf. To get other real numbers to always
display correctly we need to build a custom printing routine that adjusts
what is displayed based on the actual bits in the double.
Add the ability to print a real variable delay. They are not scaled by
the compiler.
Since a delayx delay may be variable we must always enclose this type of
delay with parenthesis.
Fix the L-value concatenation to be in the correct order.
Handle the special case that an if with a single if as the true statement
does not loose any associated else clause to the enclosed if. Basically
add a begin/end pair as needed to make things work out correctly.
Lars-Peter Clausen
Cary R
Martin Whitaker
Martin Whitaker
Larry Doolittle