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4 Commits

Author SHA1 Message Date
Stephen Williams d630e4dfe9 Elaborate VHDL entity port types/expressions. 
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
 2013-06-12 14:21:35 -07:00
Stephen Williams e927960121 Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
Stephen Williams 7f7decde03 Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
Stephen Williams d9fea802da Function declarations in packages 
This is still basic. Definitions are still not done.
 2013-06-12 14:09:07 -07:00