steve
|
424e6a750c
|
Handle unconnected module ports.
|
1999-09-17 02:06:25 +00:00 |
|
steve
|
1b858735f2
|
Elaborate module ports that are concatenations of
module signals.
|
1999-08-04 02:13:02 +00:00 |
|
steve
|
5f10342f52
|
Parse into pform arbitrarily complex module
port declarations.
|
1999-08-03 04:14:49 +00:00 |
|
steve
|
e0a988bf7e
|
Add functions up to elaboration (Ed Carter)
|
1999-07-31 19:14:47 +00:00 |
|
steve
|
3ff6912bdd
|
Elaborate user defined tasks.
|
1999-07-03 02:12:51 +00:00 |
|
steve
|
37b60a4c52
|
Clean up interface of the PWire class,
Properly match wire ranges.
|
1999-06-17 05:34:42 +00:00 |
|
steve
|
3fb7a053be
|
Introduce verilog to CVS.
|
1998-11-03 23:28:49 +00:00 |