iverilog

Commit Graph

Author	SHA1	Message	Date
Stephen Williams	f32ede23b7	Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.	2011-02-13 16:54:56 -08:00
Stephen Williams	bc5fe9676e	Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.	2011-02-13 16:54:56 -08:00

Author

SHA1

Message

Date

Stephen Williams

f32ede23b7

Do type mapping in the parser.

In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.

2011-02-13 16:54:56 -08:00

Stephen Williams

bc5fe9676e

Create the shell of a proper type system.

Rather then just relying on comparing type names all throughout
elaboration, create type description data structures and use them
during elaboration to handle proper types.

2011-02-13 16:54:56 -08:00

2 Commits