luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
8,017 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

36 Commits

Author SHA1 Message Date
Maciej Suminski 79f38b8c56 vhdlpp: Basic loop support (loop..end loop). 2016-03-07 09:54:28 +01:00
Maciej Suminski e0b2a5b337 vhdlpp: Refactored prange_t (class ExpRange). 2016-01-06 15:30:06 +01:00
Maciej Suminski 442750ca2c vhdlpp: Refactored {Report,Assert}Stmt so they handle expressions instead of strings. 2016-01-05 13:55:22 +01:00
Maciej Suminski f4238eb563 vhdlpp: Minor code cleaning. 2015-12-03 17:56:41 +01:00
Maciej Suminski 9df470c341 vhdlpp: While loops. 2015-12-03 17:53:13 +01:00
Christian Taedcke 6d5aabd4f0 Make a few constructors explicit. 
This removes cppcheck warnings.
 2015-10-22 12:33:33 +02:00
Maciej Suminski cc9b182eb6 vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
Maciej Suminski 29ddd5208f vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
Maciej Suminski 68f8007fc4 vhdlpp: 'wait for' statement. 2015-06-08 18:42:52 +02:00
Maciej Suminski cfa43c7742 vhdlpp: Support for reports & asserts. 2015-04-23 11:58:40 +02:00
Maciej Suminski 5b7b980ead vhdlpp: Support for multiple choices in case statements. 2015-02-05 12:00:25 +01:00
Maciej Suminski 9de69f2f24 vhdlpp: SequentialStmts write_to_stream() methods. 2015-02-05 11:25:03 +01:00
Maciej Suminski 25c3798248 vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture. 2015-02-04 16:57:43 +01:00
Maciej Suminski 839f9cd7ae vhdlpp: Added ReturnStmt::cast_to() method. 2015-02-04 16:57:43 +01:00
Maciej Suminski ff5b696569 vhdlpp: Improved SequentialStmt visitor. 2015-02-04 16:02:38 +01:00
Maciej Suminski e6b22a2bea vhdlpp: Visitor for SequentialStmt. 2015-02-04 16:02:38 +01:00
Maciej Suminski 0592ba042e vhdlpp: For-loop emission rewritten to handle 'range in subprograms. 2015-02-04 16:02:38 +01:00
Maciej Suminski 675b7d8efa vhdlpp: Support for std_logic_vector return type in functions. 
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
 2014-09-30 15:58:26 +02:00
Cary R d6b6b76015 Update header files to use a more standard name to prevent rereading 
This is from github report #16. There are likely a few more issues
that need to be addressed though this takes care of the major ones.
 2014-07-23 13:42:56 -07:00
Stephen Williams 164b5f9348 Fix SV emit of ForLoopStatement and ReturnStmt. 2013-06-12 14:09:07 -07:00
Stephen Williams bad8ed39c1 Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Stephen Williams 2063c5ee9d Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
Stephen Williams 8003382b3e Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams f5220c54f1 Handle variables in process statements 
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
 2011-08-17 20:19:15 -07:00
Cary R 836e61e878 Fix spacing issues in the code. 
Remove space at the end of line and space before tab since they serve
no purpose.
 2011-07-30 09:33:28 -07:00
Pawel Szostek 60deb775ca Add support for VHDL's loop statements 2011-07-12 19:20:04 -07:00
Pawel Szostek ad31eaaea8 Add parser support for VHDL's procedure call 
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
 2011-07-08 18:10:30 -07:00
Pawel Szostek 5934dcc17c Add parser support for vhdl's case-when 
Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
 2011-06-30 19:57:27 -07:00
Stephen Williams d14f60f28a Elaborate and emit vhdl elsif sections. 
The IfStatement contains a list of elsif sections that need
to be elaborated/emitted in the middle of the true and false
clauses.
 2011-06-22 18:13:40 -07:00
Stephen Williams bf40c8ecc5 Conditional statements and expressions 
Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
 2011-06-12 10:51:31 -07:00
Stephen Williams da0fb1666f Detect always @edge patterns 
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
 2011-05-28 10:49:33 -07:00
Stephen Williams a53082176d Arrange for ports used as l-values to be declared as "reg". 
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
 2011-05-15 16:17:51 -07:00
Stephen Williams fc25ccde06 Basic emit of sequential code 
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
 2011-05-15 11:07:42 -07:00
Stephen Williams 3e419dc854 Parse/decorate sequential statements. 
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.

Also add a few missing expression types.
 2011-05-08 16:40:35 -07:00