Commit Graph

10116 Commits

Author SHA1 Message Date
Martin Whitaker b9863b4fde Store user-supplied path to object in symbol_search results.
(wanted by next commit)
2021-07-31 12:42:53 +01:00
Martin Whitaker 3b1b611a18 Fix evaluation of out-of-bounds bit/part-select in constant function (issue #531). 2021-07-30 20:34:47 +01:00
Martin Whitaker 061121203b Fix segfault in wildcard port connection with unnamed port (issue #530).
A module port list may contain unnamed entries, e.g.

  module dut(a,);

When performing a wildcard connection, these entries should be skipped,
as there is no name to match.
2021-07-30 17:42:16 +01:00
Cary R 6b127432da Cleanup space 2021-06-20 22:51:32 -07:00
Cary R c07a6ec8fd Correctly dump case items 2021-06-20 22:39:43 -07:00
Cary R eb5b04626d Handle elaboration tasks with a single string argument 2021-06-20 22:03:55 -07:00
Cary R 31e3155426 Fix fprintf display type 2021-06-17 22:46:24 -07:00
Cary R bb2c51a174 Update fstapi files to latest from GTKWave 2021-06-17 21:41:36 -07:00
Martin Whitaker 1f8876be1c Fix .event/or connectivity when inputs have multiple fanout (issue #508).
The old implementation connected all inputs to the same vvp_net_t port,
on the basis that we don't care about the data values or what port they
arrived on. But if one or more of the inputs fans out to multiple nets,
the chains get tangled, which either results in connections being lost
or inappropriate connections being made, depending on the order that
the inputs are linked.

This could have been fixed by using a standard wide functor. But as we
don't care about the data values, that would be unnecessary overhead.
We just need separate vvp_net_t objects to handle the input connectivity
and can keep using a single shared functor.
2021-05-18 08:36:04 +01:00
Martin Whitaker 711623f682 Remove redundant elab_and_eval_lossless(). 2021-05-16 17:31:59 +01:00
Martin Whitaker a040ddc070 Do not force lossless calculation for index expressions (issue #515)
The standard Verilog expression bit length rules must be used.
2021-05-16 17:19:13 +01:00
Miodrag Milanovic 1341dee0e6 Fix for cross compile build 2021-05-12 09:16:11 +02:00
Martin Whitaker cf0bf4d9aa Record the actual data type when a module port has an enum type.
This fixes assignment compatibility problems (issue #498).
2021-04-28 20:18:04 +01:00
Martin Whitaker a7cb93842e Fix waveform dumpers to use vpiInstance when dumping all variables. 2021-04-21 09:23:19 +01:00
Martin Whitaker d2521878d7 Add support for vpiInstance as the type code in calls to vpi_iterate().
This is needed for the waveform dumpers now that vpi_iterate(vpiModule, NULL)
has been ficed to only return modules.

This includes recognising vpiProgram and vpiInterface, although the compiler
and vvp currently incorrectly classify them as modules.
2021-04-21 09:01:50 +01:00
Martin Whitaker 7d7aa0604c Properly report errors for out-of-bounds constant indexed part selects.
(replacing assertions)

The IEEE standard either requires out-of-bounds bits to be ignored on
write, returned as 1'bx on read, or requires a compile-time error message.
The latter is easier to implement.
2021-04-20 22:58:40 +01:00
Martin Whitaker 4af830187e Support indexed part selects that index sub-arrays (issue #497) 2021-04-20 21:29:00 +01:00
Martin Whitaker 7c024d6cab Fix width calculation for bit/part selects of multi-dimensioned packed arrays.
If we have a bit/part select that is selecting one or more sub-arrays, e.g.

  wire [3:0][3:0] foo;
  assign foo[1] = 4'd1;

we need to take into account the bit width of the sub-array when calculating
the bit width of the select.
2021-04-20 21:02:04 +01:00
Martin Whitaker 3167b2ed24 Don't return packages when iterating over root modules (issue #496)
The code assumed all handles stored in vpip_root_table were modules. This
is true for traditional Verilog, but not so for SystemVerilog.

Whilst here, also add support for iterating over packages.
2021-04-18 09:47:21 +01:00
Martin Whitaker d8cb29f6e0 Fix bug in preprocessor line directive handling. 2021-03-14 10:03:08 +00:00
Martin Whitaker 9a2c43ec34 Recognise and obey `line directives in the preprocessor (issue #488)
To correctly restore the file name and line number after including a
file or expanding a macro, the preprocessor needs to be aware of the
changes introduced by `line directives. The `line directive still
needs to be passed on to the main compiler so it can track the
changes too.

To avoid duplicate error messages, the preprocessor silently ignores
invalid `line directives, relying on the main compiler to report the
errors.
2021-03-13 23:38:30 +00:00
Martin Whitaker 45db0db8b3 Check that port default values are constant expressions. 2021-03-12 23:27:19 +00:00
Martin Whitaker c7eaa06a2b Add support for module input port default values (issue #489). 2021-03-10 08:21:42 +00:00
Cary R 60a77b08d2 Add compiler and the start of vvp support for ->> 2021-02-19 23:21:51 -08:00
Cary R 753bf516d6 Update the symbol search to find class properties 2021-02-16 23:46:02 -08:00
Cary R 18e7406dd0 Check for enum constants when declaring implicit nets 2021-02-13 23:34:09 -08:00
Cary R 2cc41a4639 Allow a macro generated string to work with an include 2021-02-13 16:58:21 -08:00
Cary R 7bb8a4463f Time literals need to be rounded using the time precision 2021-02-13 01:11:43 -08:00
Cary R 5530fbac9f Find the process name from always @(...) begin : <name> 2021-02-08 22:23:23 -08:00
Cary R 18392a464d Some clean up and add initial support for elaboration system tasks 2021-02-01 00:22:01 -08:00
Cary R 8484ff71ac Program supports NBA and BA to module variables 2021-01-30 14:28:48 -08:00
Cary R a73357ec72 Fix space issues 2021-01-30 00:47:45 -08:00
Cary R a446c34d10 Fix down parameter out of bound message 2021-01-30 00:40:25 -08:00
Cary R 0c12344b27 Fix warning and little E full vector up/down selects 2021-01-30 00:40:16 -08:00
Cary R 31a68fcd8a Report possible nested comments 2021-01-29 18:10:11 -08:00
Cary R 9e3d6cc996 Elaborate alternate constant ternary expressions to check for errors 2021-01-29 18:10:03 -08:00
Martin Whitaker 348bc13a21 CI: run 'make check' before 'make install'.
This makes sure 'make check' works when iverilog isn't already
installed on the system.
2021-01-28 00:14:00 +00:00
Martin Whitaker 56d2d798ec Don't exit when ivl_root not found - the user may have supplied it.
When running 'make check' without having an installed copy, find_ivl_root()
will fail on Unix systems that don't provide /proc/self/exe (e.g. MacOS).
2021-01-28 00:13:23 +00:00
Cary R 0cfbb8afeb Fail for `else or `elsif after a matching `else 2021-01-26 19:53:45 -08:00
Cary R f8e82448be Add a warning when a single % is at the end of the format string 2021-01-25 21:58:32 -08:00
Cary R 7e40f5ac52 Add warning when too many parameter overrides are provided for a module instantiation 2021-01-21 23:16:31 -08:00
Cary R 956f6ccf4c Update VPI routines to on error signal VVP to return non-zero 2021-01-20 23:50:53 -08:00
Cary R 21c5fbe759 Remove compile warnings 2021-01-18 13:15:12 -08:00
Cary R d1eb4befcc Add initial parsing for let construct 2021-01-18 13:06:44 -08:00
Stephen Williams a19caf4fe6 Actions: only test on pushes to master.
Continue to test all pull requests, but only retest pushes to
master so that work in progress prs don't create quite as much
test traffic.
2021-01-18 12:43:24 -08:00
Stephen Williams 9b432ba172 Implement vpiSize method for stack string values.
This might come to pass for example when calling the function
$ivl_string_method$len(<expression>) where the expression is
calculated, and not simply a variable name.
2021-01-18 12:39:54 -08:00
Stephen Williams 287ba56ab4
Merge pull request #473 from steveicarus/steveicarus/queue-element-expressions
Rework of elaboration of function calls.
Rework of symbol_lookup function and API.
2021-01-18 11:58:26 -08:00
Stephen Williams 38b3c8efb2 Rework symbol_search function.
There are too many ad hoc handlers of symbol_search partial results.
Rewrite symbol_search to clean up things like partial results and
member/method detections. Use this reworked symbol_search function
to rewrite expression elaborate for the PECallFunction expressions.
2021-01-17 19:33:52 -08:00
Cary R e02410d519 Add define to indicate Icarus synthesis 2021-01-14 00:15:48 -08:00
Cary R 7dc65af362 Add support for zero-based variable index part selects in a CA 2021-01-11 23:26:34 -08:00