Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
Stephen Williams
Cary R
steve