ca9616dc7b
Better simple_expression parse rules.
2013-06-12 14:21:36 -07:00
24bd630cb2
Parse (to sorry messages) unbounded array definitions.
2013-06-12 14:21:36 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
7556a37859
Parse function calls, and detect type case expressions.
...
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
836e61e878
Fix spacing issues in the code.
...
Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
...
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
830b7cf122
Add basic instantiation list handling in VHDL
...
A class for representing instantiation list has
been added.
2011-04-02 09:27:58 -07:00
26e6865bef
Add entity aspects to VHDL parsing
...
Entity aspects are now recognized and parsed
into corresponding objects. A new class (entity_aspect)
has been added.
2011-04-01 17:03:45 -07:00
abb03632dd
Basic elaboration of vhdl component instantiations.
...
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
2011-03-31 19:07:43 -07:00
Stephen Williams
Arun Persaud
Cary R
Pawel Szostek
Pawel Szostek