This patch adds a flag -pallowsigned=1 to the vlog95 converter that
tells it to allow signed signals. There is currently no code to check
for and warn/emit the $signed() and $unsigned() system functions. I
need to determine if >>> emitting should also be controlled by the
allow signed flag.
This patch adds a flag that emits file and line information for
most lines. This can help the user understand where the various
lines came from in the original code. They are printed as
comments so the generated code still runs correctly.
This patch adds the following to the vlog95 converter.
Add support for emitting and calling UDPs.
Generate a UDP for a synthesized DFF.
Add the ability do emit a constant assigned to a net.
This patch adds the ability for the user to change the spacing increment
from the command line using the -pspacing=<num> flag. The is restricted to
be a value between and including 1 and 16.
This patch adds significantly more functionality to the vlog95 back end.
The following are the major additions:
Display unsigned numbers without undefined bits in hex.
Add support for both L-Value and R-value bit and part selects.
Added support for out of scope references.
Added support for emitting logic gates (range not finished, name is invalid).
Added support for emitting initial/always blocks.
Add support for event inter statement delays.
Convert a blocking inter statement delay assign back to the original form.
Added support for rescaling variable delays.
Added support for the disable statement.
Added support for an event trigger statement (event name is missing).
Added support for calling a user task (calling arguments are missing).
Added support for an event based delay statement (@) (event name is missing)
Not all of these are working as expected since there is not currently a
routine to find a nexus name as a function of scope (needed for event names,
logic gate ports, etc.). Since the Icarus compiler generates structural code
the arguments to modules, module instantiations and calling user tasks are
also still missing.
This patch adds support for the various case statements and adds
preliminary support for instantiating modules. The module instantiation,
just like the module definition, is still missing ports. Adding this
will require modification to the compiler to get the port order correct.
Because of defparams and passed parameters any module that has a
parameter must be generated uniquely for each instance since they may not
all be the same. Modules without parameters are only generated once.
This patch adds more support to the Verilog 1995 converter. There is
still a lot that is missing and there is still some implemented
functionality that is not 100%.
This is the initial commit in an effort to build a 1364-1995
back end for Icarus Verilog. It is expected that this back end
will allow the user to write 1364-2005 RTL and then using this
back end (converter) generate functionally equivalent 1364-1995
compatible code. This can be used to support older tools in a
work flow. The primary focus will be simulation equivalence,
though I expect to verify logical equivalence as well.
Cary R