Add a new compile-time code-generator target that exports the elaborated
design as a JSON dataflow database (schema flowtracer1.merged.v0), shared
with the GHDL --flow exporter so a single consumer works across Verilog
and VHDL designs.
The exporter walks the elaborated netlist via ivl_target.h and emits:
- modules[] keyed by module type, with ports/generics/signals and
name-based processes[] and assignments[] (reads/drives/sensitivity
as signal names);
- hierarchy[] with port_map associations resolved through the shared
nexus, and generate blocks as transparent scope:true frames;
- a secondary integer-id nets[]/cells[] graph (drivers/loads,
clocked/clock_net).
Process reads/drives come from walking the statement/expression tree;
continuous assigns are recovered from logic/LPM devices with transitive
backward-cone resolution through synthetic nets. Generate scopes are
transparent to dataflow attribution and to port-map actual resolution.
Wired into the build (SUBDIRS, configure.ac), documented in
Documentation/targets/tgt-flow.rst, and covered by ivtest/flow_reg.py
(flow_basic, flow_comb, flow_generate, flow_genpath).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
William P. Moore