8298c96dee
vhdlpp: Turned elaborate_argument() into a SubprogramHeader method.
2016-03-07 09:54:28 +01:00
00f5785f2c
vhdlpp: Minor changes to write_to_stream functions.
2016-03-07 09:54:28 +01:00
2606d0e897
vhdlpp: Minor code clean up.
2016-03-07 09:54:28 +01:00
3b310e8227
vhdlpp: Elaborate subprograms in packages.
2016-01-05 14:23:25 +01:00
46ea9e6954
vhdlpp: Out & inout arguments in subprogram calls are turned to registers.
...
Otherwise it is not possible to modify their values in subprograms.
Argument elaboration has been moved to a separate function, so now it is
common for procedure and function calls.
2015-12-01 10:32:47 +01:00
6d5aabd4f0
Make a few constructors explicit.
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This removes cppcheck warnings.
2015-10-22 12:33:33 +02:00
cc9b182eb6
vhdlpp: Procedure calls.
2015-06-24 23:53:32 +02:00
b666b9c0bf
vhdlpp: Fixed a few memory leaks.
2015-06-24 23:53:32 +02:00
169228ad0f
vhdlpp: Refactored the way of handling standard VHDL library functions.
2015-06-24 23:53:31 +02:00
47c5ce0ab6
vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody.
2015-06-24 23:53:31 +02:00
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
5349ca9a55
vhdlpp: Added Subprogram::write_to_stream_body() method.
2015-02-05 12:00:25 +01:00
1a367c84b6
vhdlpp: Subprograms can have instances that take a different set of parameter types.
2015-02-05 11:25:03 +01:00
48265ecd9b
vhdlpp: Subprograms return types have their ranges evaluated if possible.
...
Added VTypeArray::evaluate_ranges() method.
2015-02-05 11:24:59 +01:00
90293d8e0a
vhdlpp: VTypeArray::is_variable_length() uses ScopeBase to determine if variable has constant length.
2015-02-04 16:57:43 +01:00
6d75af86e6
vhdlpp: Added Subprogram::fix_variables() method.
2015-02-04 16:57:43 +01:00
2ecfed0baa
vhdlpp: Moved part of check_unb_vector() to fix_logic_darray().
2015-02-04 16:57:43 +01:00
c287281bbe
vhdlpp: Tries to determine if function return type is fixed size.
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Added Subprogram::fixed_return_type() method.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
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We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
d9fea802da
Function declarations in packages
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This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
Maciej Suminski
Christian Taedcke
Cary R
Stephen Williams