442750ca2c
vhdlpp: Refactored {Report,Assert}Stmt so they handle expressions instead of strings.
2016-01-05 13:55:22 +01:00
9df470c341
vhdlpp: While loops.
2015-12-03 17:53:13 +01:00
cc9b182eb6
vhdlpp: Procedure calls.
2015-06-24 23:53:32 +02:00
29ddd5208f
vhdlpp: 'wait on' and 'wait until' statements.
2015-06-08 18:42:52 +02:00
68f8007fc4
vhdlpp: 'wait for' statement.
2015-06-08 18:42:52 +02:00
cfa43c7742
vhdlpp: Support for reports & asserts.
2015-04-23 11:58:40 +02:00
5b7b980ead
vhdlpp: Support for multiple choices in case statements.
2015-02-05 12:00:25 +01:00
839f9cd7ae
vhdlpp: Added ReturnStmt::cast_to() method.
2015-02-04 16:57:43 +01:00
ff5b696569
vhdlpp: Improved SequentialStmt visitor.
2015-02-04 16:02:38 +01:00
e6b22a2bea
vhdlpp: Visitor for SequentialStmt.
2015-02-04 16:02:38 +01:00
bad8ed39c1
Parse VHDL subprogram bodies and return statements.
2012-11-03 09:54:07 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
f5220c54f1
Handle variables in process statements
...
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
de356b03c8
Fix most of the cppcheck warnings in the vhdlpp directory.
...
Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
836e61e878
Fix spacing issues in the code.
...
Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
...
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
5934dcc17c
Add parser support for vhdl's case-when
...
Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
2011-06-30 19:57:27 -07:00
bf40c8ecc5
Conditional statements and expressions
...
Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
2011-06-12 10:51:31 -07:00
da0fb1666f
Detect always @edge patterns
...
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
2011-05-28 10:49:33 -07:00
3e419dc854
Parse/decorate sequential statements.
...
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.
Also add a few missing expression types.
2011-05-08 16:40:35 -07:00
Maciej Suminski
Stephen Williams
Arun Persaud
Cary R
Pawel Szostek