2 Commits

Author	SHA1	Message	Date
Lars-Peter Clausen	472598dd74	Report errors for nets with invalid data type ... While a variable can have any data type the data type for nets is quite restricted. The SystemVerilog LRM section 6.7.1 ("Net declarations with built-in net types") requires that the data type of a wire is either a 4-state packed or a unpacked struct or unpacked array of 4-state packed types. As an extension to this iverilog allows real data type for wires as well as 2-state packed types. Add a check that reports an error if a net with any other type is declared. In addition in Verilog a net can not have an explicit data type at all. It can only have a packed dimension and a signed flag. As an extension to this Icarus also allows wires to be of `real` data type. Note that in Verilog mode the data type is checked in the parser since only the parser knows whether the data type is an implicit type (`input reg [7:0]` and `input [7:0] x` elaborate the same). But for SystemVerilog the type is checked during elaboration since due to forward typedefs and type parameters the type is not necessarily known in the parser. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2022-03-03 10:30:12 +01:00
Stephen Williams	cea237b407	Add ivtest to the iverilog source tree ... By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.	2022-01-15 10:18:50 -08:00