Commit Graph

16 Commits

Author SHA1 Message Date
Martin Whitaker 465e0d2710 Allow classes to reference declarations in their enclosing scope(s).
The original implementation made each class a root scope. They should
be added to the scope hierarchy just like any other declaration.
2019-12-22 10:46:38 +00:00
Martin Whitaker 988816c0b1 Support separate compilation units in SystemVerilog.
The compilation unit scope is now treated as a specialised form of
package (with an automatically generated name). All items declared
outside a design element are added to the current compilation unit
package. Apart from when searching for a symbol, once we get into
elaboration we can treat these just like any other package.
2017-10-31 20:38:59 +00:00
Stephen Williams 338a0eb11a Get $root scope tasks/fuctions down to the ivl_target API. 2014-10-02 14:09:27 -07:00
Cary R d6b6b76015 Update header files to use a more standard name to prevent rereading
This is from github report #16. There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
Stephen Williams b4dbb81af7 Fix handling of certain constants in ivl_target.h API.
The construction of the ivl_design_t consts member was broken,
not properly handling the addition of new objects.
2013-08-01 17:28:04 -07:00
Stephen Williams fb23493a98 Class methods down to the code generator
Emit the elaborated class methods. Also generate root scopes to
represent the classes in order to hold the methods. These scopes
can also in the future be used to implement static properties.
2013-03-24 15:12:35 -07:00
Stephen Williams 60cb78e4ab Add packages and their own scope.
This makes <pkg>::<name> work properly, and also makes the
package descriptions available through VPI.
2013-02-17 17:00:15 -08:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Stephen Williams 79f8b8fcfd Remove Link::strength_t and PGate::strength_t types.
These types are useless repetition of the ivl_drive_t type.
This is also another chapter in the series to push ivl_target
generation further upstream.
2010-03-16 15:16:53 -07:00
Stephen Williams 16e5197325 Branches are parts of islands.
Expose the island information for branches to the ivl_target API.
2008-11-24 22:00:33 -08:00
Stephen Williams 87177087c4 ivl_target.h access branch terminals
Fill in the functions to add branch terminals, and add code in the
stub to check that the terminals are present and reasonable.
2008-11-23 22:38:33 -08:00
Stephen Williams d8ec6fc42a Add functions for targets to scan disciplines.
The disciplines are, from the perspective of the ivl target, collected
into the design. Add functions for the target to scan the disciplines
in the design.

In the process, also clean up the handlng of design constants.
2008-11-23 21:29:54 -08:00
Stephen Williams da85c4fe00 Give the branch access expression type some meat.
In the ivl_target API, the IVL_EX_BACCESS expression type gets some meat,
specifically references to the branch it accesses and the the nature to
be accessed on that branch.
2008-11-11 20:41:14 -08:00
Stephen Williams 00df651c5f Branch references all the way down to the stub generator.
This includes enough API to get the branch nexus bits and signals
and show them in the dump. This also includes creating the reference
ground for branch access functions that use the implicit ground.
2008-11-09 21:42:12 -08:00
Stephen Williams 0da27a2f45 Collect analog branches into islands.
Discipline islands all along were intended to carry collections of
analog branches, as well as the current switch modeling support.
2008-11-09 15:32:50 -08:00
Stephen Williams df15a0368c Collect NetTran devices into islands.
NetTran devices must be collected into islands because they are all
a bi-directional mass. This is how vvp will process them and the code
generator will need a head start organizing them.
2008-06-01 19:45:12 -07:00