9125a4c451
Careful with wires connected to multiple ports.
2000-01-09 20:37:57 +00:00
2de887c2ff
Support named parameter override lists.
2000-01-09 05:50:48 +00:00
3e1738dcec
Fix support for attaching attributes to primitive gates.
1999-12-11 05:45:41 +00:00
4cfa3e4047
Support the creation of scopes.
1999-11-27 19:07:57 +00:00
9eae940ebd
Parameter overrides support from Peter Monta
...
AND and XOR support wide expressions.
1999-08-23 16:48:39 +00:00
1b858735f2
Elaborate module ports that are concatenations of
...
module signals.
1999-08-04 02:13:02 +00:00
5f10342f52
Parse into pform arbitrarily complex module
...
port declarations.
1999-08-03 04:14:49 +00:00
e0a988bf7e
Add functions up to elaboration (Ed Carter)
1999-07-31 19:14:47 +00:00
3ff6912bdd
Elaborate user defined tasks.
1999-07-03 02:12:51 +00:00
d0afc9adee
Get rid of the STL vector template.
1999-06-15 03:44:53 +00:00
e2a37a8ccd
Add support for module parameters.
1999-02-21 17:01:57 +00:00
fb439c78b9
Add the LineInfo class to carry the source file
...
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
1999-01-25 05:45:56 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve