Nick Gasson
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041925c123
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Component instantiation to replicate Verilog hierarchy
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2008-06-02 17:45:58 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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5cbd587833
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Clean up generated objects
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2008-05-31 16:08:57 +01:00 |
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Nick Gasson
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8189c4ee43
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Generate VHDL entities and architectures for all module scopes
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2008-05-31 15:28:25 +01:00 |
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Nick Gasson
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e38494a10c
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Pretty-print VHDL output
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2008-05-29 16:24:16 +01:00 |
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Nick Gasson
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bfa2bfc8ae
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Makefile and autoconf changes to build VHDL code generator
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2008-05-28 17:17:39 +01:00 |