Testing with 32-bit clang 3.3, with additional compiler flags
-Wsign-compare -Wundef
this patch eliminates the following warnings:
config.h💯6: warning: 'UINT64_T_AND_ULONG_SAME' is not defined, evaluates to 0 [-Wundef]
vcd_priv2.cc:233:12: warning: duplicate 'extern' declaration specifier [-Wduplicate-decl-specifier]
parse.cc:6496:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6499:13: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6502:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6510:53: warning: comparison of integers of different signs: 'const unsigned int' and 'int' [-Wsign-compare]
Changing the vlltype elements from unsigned to int reconciles their
type with the native bison YYLTYPE structure.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
This patch is based on one from "bruce <bruce1914@gmail.com>".
I've applied all but the elaboration code, which I rewrote to
properly work with the elaboration work queue. I also constrained
the implementation so that the parameter name must have exactly
two components: the root scope name and the parameter name. This
is necessary to keep the defparm processing sane. The comments
from bruce's original patch are as follows:
--
This patch would provide function to define parameter from command
line. This serves the same functionality as 'defparam' in Verilog
source code, but provide much more ease for using. Parameter
definition can be write in command file, with following syntax:
+parameter+<scope>.<parameter>=<val>
*Do not apply any space between them*
The scope name should be full hierachical name with root name at
the begining. The following example would override test.T1 with
new value 2'b01:
+parameter+test.T1=2'b01
'test' here is the root module name. The parameter value here
should be constant. Parameter definition can also be write in
the command line:
iverilog -Ptest.T1=2'b01
This serves the same functionality with the previous example.
If we define the same parameter in command file and command line,
the one in command line would over-write all others.
This patch modifies the original SystemVerilog timeunit/timeprecision
patch in the following way:
Removed trailing space.
Reworked some code to use standard spacing rules.
Added some comments.
Combined some code.
Major rework of local/global timeunit/timeprecision logic.
Major rework of timeunit/timeprecision declaration/check code.
This was needed to remove the shift/reduce warnings.
Add a number of checks for invalid combinations.
This patch cleans up some unneeded code. Releases some allocated
memory before the compiler quits and fixes a couple minor memory
leaks in the compiler and vvp code generator.
Icarus has recognized this directive, but it did not do anything
with the information. This patch adds the functionality for most
common cases. It adds this by changing the input net type from
wire/tri to tri1 or tri0 depending on the pull. The issue is that
if the input net is not a wire or tri this is not safe and should
really be done as an external pull gate connected to the input.
We will need to handle this is it ever comes up. For now a sorry
message is printed.
This patch adds real functionality for `celldefine and pushes this
property to the run time which can access this with vpiCellInstance.
This is technically only available for a module, but all scopes
have the property and only modules should return true when the
'endmodule' is between a `celldefine and `endcelldefine directive.
Remove the #ident and $Log$ strings from all the header files and
almost all of the C/C++ source files. I think it is better to get
this done all at once, then to wait for each of the files to be
touched and edited in unrelated patches.
Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
Cary R
Larry Doolittle
Stephen Williams
Arun Persaud
steve