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iverilog
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8 Commits

Author SHA1 Message Date
steve 1b858735f2 Elaborate module ports that are concatenations of 
module signals.
 1999-08-04 02:13:02 +00:00
steve 5f10342f52 Parse into pform arbitrarily complex module 
port declarations.
 1999-08-03 04:14:49 +00:00
steve e0a988bf7e Add functions up to elaboration (Ed Carter) 1999-07-31 19:14:47 +00:00
steve 3ff6912bdd Elaborate user defined tasks. 1999-07-03 02:12:51 +00:00
steve d0afc9adee Get rid of the STL vector template. 1999-06-15 03:44:53 +00:00
steve e2a37a8ccd Add support for module parameters. 1999-02-21 17:01:57 +00:00
steve fb439c78b9 Add the LineInfo class to carry the source file 
location of things. PGate, Statement and PProcess.

 elaborate handles module parameter mismatches,
 missing or incorrect lvalues for procedural
 assignment, and errors are propogated to the
 top of the elaboration call tree.

 Attach line numbers to processes, gates and
 assignment statements.
 1999-01-25 05:45:56 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00