This patch converts a constant real index to an integer value when
defining an array. This can happen when using 2**8 which returns a
real value since the operands are signed.
draw_number_bool64() in tgt-vvp/eval_bool.c was using %ix/load to
load immediate values into registers greater than three. The problem
was that of_IX_LOAD() in vvp/vthread.cc was masking off the upper
bits. This was putting the results in the wrong register. This patch
removes the bit masking from of_IX_LOAD() and updates the %ix/load
documentation.
The file lexor.lex was beginning to suffer a catastrophic
increase in entropy due mainly to the mingling of spaces
and tabs--an age-old problem that often finds itself as
the subject of many a religious war.
The key rule: Make it consistent in as many editors as
possible; this was achieved by converting all hard tabs
into soft tabs (composed of spaces) of width 4.
I couldn't help but make modifications to the code as I
tabifified, but most of the changes are strictly style.
While maintainers generally treat large scale whitespace and
formatting changes with much caution, I believe that the code
is now much more maintainable; moreover, the test suite
produces the same results as before.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Macro names cannot be compiler directive names.
Such trespasses are now recognized and reported:
(1) Offending `define lines are skipped.
(2) Offending macros meant to be expanded
are replaced with nothing.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
The ordering of the logic was a little strange before.
Also, there were unnecessary operations, like the assert
and the include_dir[0]=0 business.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
Discussions online and "standards" documents are never
conclusive, but the code that was present suggests that
iverilog adopts the sane practice of resolving relative
paths against the directory of the file that is currently
being processed.
Unfortunately, when a relative path is made absolute, the
code forgot to update the necessary include_stack_t object.
This has now been fixed.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
When the lexical analyzer encounters and EOF, the
analyzer invokes yywrap() to determine what to do
next. The function determines one of two paths of
execution:
(1) If yywrap() returns 0, then the analyzer
assumes that yywrap() has setup a new input
source, and so scanning continues.
(2) If yywrap() returns non-zero, then the analyzer
assumes that yywrap() has not setup a new input
source, and so the analyzer proceeds to run the
matching EOF action (the default of which invokes
yyterminate()).
NOTE: The analyzer does not touch the start condition.
The old implementation was using yywrap() to destroy the current
input source and setup the next one. However, this causes problems
when the analyzer is in the middle of parsing some directive:
(1) Because yywrap() is called before any EOF action,
the include_stack_t structure is destroyed before
being used in the EOF action; the result is a segfault.
(2) Because yywrap() does not change the start condition,
any EOF action would occur completely out of context;
however, because of (1), this problem never cropped
up.
The new implementation simply:
(1) Employs "%option noyywrap", which effectively causes
the analyzer to act as though yywrap() produces a non-zero.
(2) Renames yywrap "load_next_input".
(3) Calls load_next_input() explicitly in exhaustive EOF actions,
so that control is more fine grained.
The added benefit is that the code that finishes parsing EOF terminated
directives now works properly; `include and `define directives previously
segfaulted in such situations.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
This variable was used in yywrap purportedly to obviate
hidden access to a file that should be closable.
After investigating the code flex produces, it would
seem that these fears are unfounded.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
The verilog preprocessing language is sufficiently simple
that the parser may be implemented by hand on top of the
lexical analyzer.
In fact, ivlpp was already implemented in this way; relevant
[bison] parser files specified no grammar, and the parser
entry-point (yyparse) was simply an indirect use of the lexical
analyzer (yylex).
Therefore, parse.y has been removed, invocations of yyparse()
have been replaced by yylex(), references to bison generated
files have been removed, and Makefile.in has been updated
accordingly.
Signed-off-by: Michael Witten <mfwitten@mit.edu>
This patch fixes two problems. The first is that thr_check_addr()
was being used inconsistently. It should be passed a real address,
but the resize of the vector should be at least one more than this
address. The extra and unneeded CPU_WORD_BITS was also removed
from the routine.
The second problem involved an invalid memory access in
vvp_vector4_t::set_vec() when the vector being copied was an integer
multiple of the machine word width. Under this condition there would
be no remaining bits that needed to be copied but the routine was always
trying to copying some remaining bits. This code is now only executed
when there is a remainder.
Neither of these appear to be causing runtime problems. The second one
was found with valgrind. The first were found while tracking down the
second problem.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
This patch adds support for delaying constants at time zero. It also
cleans up the code in elab_net.cc to use this capability instead of
building it with an extra BUFZ to carry the delay information.
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
This patch adds a real error message instead of an assert when
someone attempts to release a part or bit select. I plan to work
on the real functionality soon.
This patch adds the power operator for signed bit based values
in a continuous assignment. It also fixes a few other power
expression width problems. The expression width is still not
calculated correctly, since the correct method can produce huge
possible bit widths. The result is currently limited to the width
of the native long. This is because lround() is used to convert
from a double to an integer. A check in the code generator protects
the runtime from this limitation.
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
User functions called in a continuous assignment were not getting
their scope mangled. This is needed to handle arrayed instances and
possibly other things.
This patch fixes some bugs in the implementation of signed integer
division with wide operands in constant expressions and adds support
for signed integer modulus with wide operands in constant expressions.
It also removes a few redundant lines of code.
Incorrect trimming of unsigned verinum values was causing the
compilers unsigned constant verinum pow function to give
incorrect results. This patch restores the pow compile time
optimization and fixes the trimming to always leave a single
zero in the MSB.
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
Currently, if a localparam declaration does not include a type or
range, the RHS expression is cast to an unsigned value. This patch
changes this to make the localparam inherit the type of the RHS
expression, as is done for parameter declarations and is specified
by the Verilog-2001 standard.
Cary R
Stephen Williams
Michael Witten
Larry Doolittle
Martin Whitaker