This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
The default nettype was not always being set. This patch
modifies the NetScope constructor to get the default
nettype from a parent if it exists. It is set to NONE if
a parent does not exist.
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
NetTaskDef and NetFuncDef functions are created during
signal enaboration, and carry these objects in the
NetScope class instead of the extra, useless map in
the Design class.
Cary R
Stephen Williams
Larry Doolittle
Martin Whitaker
steve