If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
Stephen Williams
steve