The Verilog LRM specifies that it is legal to give constant part
selects that are beyond the bounds of the identifier being selected.
But elaboration was flagging that as an error. This patch changes it
to a warning, and handles the cases by generating 'bx bits as needed.
When left-shifting unsized constants in self-determined contexts, the
constant value is normally pared down to its minimum required width.
But this practically guarantees loss of bits. Instead, detect this
special case and give the unsized constant a width of an integer.
Still allow for the super-special case that the shifted value and the
shift amount are constants. In that case, the result width (and value)
can be calculated precisely and there is no need to resort to default
widths.
It is questionable, but probably legal, for expressions passed as
arguments to input ports of various kinds of gates to implicitly
declare nets. This patch allows the scan through different types
of expressions for implicit nets.
The elaborate_sig handling here does not test for the legality of
having a non-trivial expression as argument to a port. For example,
it is definitely NOT legal to have r-value expressions passed to
output or inout ports. But that will be checked for later when the
instance is elaborated for real.
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
Comparison operands are signed only of both operands are signed.
If one is unsigned, then they both are unsigned. This does not
affect the signedness of the comparison itself, which is unsigned.
Signed-off-by: Stephen Williams <steve@icarus.com>
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
The argument to $unsigned is self-determined no matter what the
context the $unsigned itself is in. This is important only where
the result can be negative but the result width is context-determined.
Do ocntext fitting manually to prevent the context fitting it and
affecting the expression argument.
Signed-off-by: Stephen Williams <steve@icarus.com>
In expressions, user defined functions have a clearly defined
width and the test_width expression needs to express that. Note
that the $signed/$unsigned functions are special and magical.
Signed-off-by: Stephen Williams <steve@icarus.com>
Non-constant indexed part select in continuous assignment generates
a select node with the correct width. In the process factor out and
share some of the part select calculations with expr part select
handling methods.
Signed-off-by: Stephen Williams <steve@icarus.com>
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
Stephen Williams
Cary R
Larry Doolittle
steve