steve
|
295306aad5
|
emit NetAssignMem objects in vvm target.
|
1999-05-12 04:03:19 +00:00 |
|
steve
|
41f9a84a4b
|
Handle much more complex event expressions.
|
1999-05-01 02:57:52 +00:00 |
|
steve
|
09cfbc6240
|
Core handles subsignal expressions.
|
1999-04-25 00:44:10 +00:00 |
|
steve
|
5895d3c98d
|
Add memories to the parse and elaboration phases.
|
1999-04-19 01:59:36 +00:00 |
|
steve
|
30a3953c85
|
Turn the NetESignal into a NetNode so
that it can connect to the netlist.
Implement the case statement.
Convince t-vvm to output code for
the case statement.
|
1999-02-08 02:49:56 +00:00 |
|
steve
|
e097c999d5
|
Elaborate UDP devices,
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
|
1998-12-01 00:42:13 +00:00 |
|
steve
|
ebad845fc3
|
Add procedural while loops,
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
|
1998-11-09 18:55:33 +00:00 |
|
steve
|
b118634189
|
Handle procedural conditional, and some
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
|
1998-11-07 17:05:05 +00:00 |
|
steve
|
3fb7a053be
|
Introduce verilog to CVS.
|
1998-11-03 23:28:49 +00:00 |