With a pattern rule, the recipe will only be executed once, even when
the rule has multiple targets. Using this to handle the output from
bison is included as an example in the GNU make manual.
This fixes the makefiles so that bison-generated header files will be
regenerated if they are deleted.
Note we only want these enabled when building the compiler and runtime
binaries. If we included the ICARUS_VPI_CONST definition in the global
CPP_FLAGS, that would propagate to the flags used by iverilog-vpi, so
would affect compilation of user VPI code.
(cherry picked from commit 542fe2cf77)
- allow ICARUS_VPI_CONST to be pre-defined by the user
- use it for sizetf as well as for compiletf and calltf
- fix remaining warnings when it is defined as 'const'
(cherry picked from commit 0d494da702)
Currently $display et al. output nothing when the expression
corresponding to a %c format specification has the value 0. As
Verilog provides no other way to write raw bytes to a file, we
should allow 0 values to be written. Other simulators allow this.
(cherry picked from commit b066a5815e)
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
(cherry picked from commit 7bed181f68)
First and second areas were changed for "Microsoft Visual Studio Express 2015 RC Web" so that gold files would match. For the third area of change, "Microsoft Visual Studio Express 2015 RC Web" wanted to print 6 zeros after the decimals for the values of 0.0 and -0.0, and then the gold files wouldn't match.
Conditions to detect rising/falling edges were incorrect.
VHDL standard specifies it has to detect the current value,
rather than compare against the previous one.
Martin Whitaker
Cary R
Larry Doolittle
Frederick C. Kurz
Maciej Suminski
Stephen Williams
Martin Whitaker