62 Commits

Author	SHA1	Message	Date
steve	853ad247a1	Elaborate and supprort to vvm the forever ... and repeat statements.	1999-06-19 21:06:16 +00:00
steve	fabb146342	Support case expression lists.	1999-06-15 05:38:39 +00:00
steve	740c63291a	l-value part select for procedural assignments.	1999-06-13 23:51:16 +00:00
steve	7605a7b1f0	Add parse and elaboration of non-blocking assignments, ... Replace list<PCase::Item*> with an svector version, Add integer support.	1999-06-06 20:45:38 +00:00
steve	5de9b7c9f1	Parse and elaborate the concatenate operator ... in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.	1999-05-10 00:16:57 +00:00
steve	ce49708442	Parse OR of event expressions.	1999-04-29 02:16:26 +00:00
steve	8bdd381cdf	Parse and elaborate the Verilog CASE statement.	1999-02-03 04:20:11 +00:00
steve	fb439c78b9	Add the LineInfo class to carry the source file ... location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.	1999-01-25 05:45:56 +00:00
steve	6b2fa19429	Handle while loops.	1998-11-11 03:13:04 +00:00
steve	ebad845fc3	Add procedural while loops, ... Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.	1998-11-09 18:55:33 +00:00
steve	b118634189	Handle procedural conditional, and some ... of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.	1998-11-07 17:05:05 +00:00
steve	3fb7a053be	Introduce verilog to CVS.	1998-11-03 23:28:49 +00:00