Martin Whitaker
ecbbb60fb6
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 16:55:03 +00:00
Maciej Suminski
25f4a54852
vhdlpp: Subprograms are matched once. ExpFunc::probe_type() return exact type
2016-09-01 12:08:44 +02:00
Maciej Suminski
163a913559
vhdlpp: Specify lifetime for variables.
2016-03-29 11:27:14 +02:00
Maciej Suminski
b7d263462c
vhdlpp: Fixed automatic variables initalization in subprograms.
2016-03-29 11:27:14 +02:00
Maciej Suminski
9d487c6951
vhdlpp: Fixed a few shadow warnings.
2016-03-12 12:03:17 +00:00
Maciej Suminski
94f7504372
vhdlpp: Subprograms are linked to Package instead of generic Scope.
2016-03-07 17:11:53 +01:00
Maciej Suminski
2c4deee0c3
vhdlpp: Support for subprogram overloading.
2016-03-07 09:54:28 +01:00
Maciej Suminski
ad5b003488
vhdlpp: Improved handling for subprogram-related errors.
2016-03-07 09:54:28 +01:00
Maciej Suminski
8298c96dee
vhdlpp: Turned elaborate_argument() into a SubprogramHeader method.
2016-03-07 09:54:28 +01:00
Maciej Suminski
3b165a5f25
vhdlpp: Skip package name emission when calling functions from the same package.
2016-03-07 09:54:28 +01:00
Maciej Suminski
f1c07b86a3
vhdlpp: Implemented ReturnStmt::elaborate() method.
2016-03-07 09:54:28 +01:00
Maciej Suminski
2606d0e897
vhdlpp: Minor code clean up.
2016-03-07 09:54:28 +01:00
Maciej Suminski
3b310e8227
vhdlpp: Elaborate subprograms in packages.
2016-01-05 14:23:25 +01:00
Maciej Suminski
46ea9e6954
vhdlpp: Out & inout arguments in subprogram calls are turned to registers.
...
Otherwise it is not possible to modify their values in subprograms.
Argument elaboration has been moved to a separate function, so now it is
common for procedure and function calls.
2015-12-01 10:32:47 +01:00
Maciej Suminski
169228ad0f
vhdlpp: Refactored the way of handling standard VHDL library functions.
2015-06-24 23:53:31 +02:00
Maciej Suminski
47c5ce0ab6
vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody.
2015-06-24 23:53:31 +02:00
Maciej Suminski
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
Maciej Suminski
5349ca9a55
vhdlpp: Added Subprogram::write_to_stream_body() method.
2015-02-05 12:00:25 +01:00
Maciej Suminski
1a367c84b6
vhdlpp: Subprograms can have instances that take a different set of parameter types.
2015-02-05 11:25:03 +01:00
Maciej Suminski
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
Maciej Suminski
6d75af86e6
vhdlpp: Added Subprogram::fix_variables() method.
2015-02-04 16:57:43 +01:00
Maciej Suminski
2ecfed0baa
vhdlpp: Moved part of check_unb_vector() to fix_logic_darray().
2015-02-04 16:57:43 +01:00
Maciej Suminski
c287281bbe
vhdlpp: Tries to determine if function return type is fixed size.
...
Added Subprogram::fixed_return_type() method.
2015-02-04 16:57:43 +01:00
Maciej Suminski
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
Maciej Suminski
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
Maciej Suminski
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
Maciej Suminski
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
Maciej Suminski
7b5470c8a7
vhdlpp: Subprogram class inherits from ScopeBase.
2014-09-30 15:00:55 +02:00
Cary R
d6b6b76015
Update header files to use a more standard name to prevent rereading
...
This is from github report #16 . There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
Stephen Williams
d630e4dfe9
Elaborate VHDL entity port types/expressions.
...
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
Stephen Williams
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
Stephen Williams
7f7decde03
Basic structure for emitting packages.
2013-06-12 14:09:07 -07:00
Stephen Williams
d9fea802da
Function declarations in packages
...
This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00