2e8c4e3dbc
Basic patch from github #44
2014-11-04 11:39:01 -08:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
41601696cc
properly handle vhdl open ports in component instantiations.
2011-06-12 16:59:07 -07:00
98f5ed2f85
Fix remaining space issues.
2011-03-14 16:26:31 -07:00
5fe889a7b4
Fix various formatting errors and typos
...
Some of these typos were fatal, bug generated only a warning
from the compiler.
2011-02-11 09:15:36 -08:00
0395eadbc8
Introductory changes for numbers handling
2011-02-10 18:34:13 -08:00
75203dc121
Minor changes to VHDL lexor
2011-02-10 18:33:53 -08:00
ac28743eb0
New keywords to lexer added and typos corrected
2011-02-10 18:33:07 -08:00
02820c9e34
Parse create entities with ports
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Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
04b239a5fb
Flesh out VHDL parser engine.
...
Add enough rules to parse a simple VHDL program:
Parse library and use clauses,
Parse entity declarations, and
Parse architecture bodies.
Add some parser infrastructure:
Handle syntax errors with useful error messages,
Include file name and line numbers in parse errors,
Add some parser debug aids.
2011-01-18 17:03:51 -08:00
8cf1fd1820
Introduce shell of vhdlpp program.
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Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00
Cary R
Maciej Suminski
Stephen Williams
Pawel Szostek