steve
ddd36ecb6c
Rework the heirarchical identifier parse syntax and pform
...
to handle more general combinations of heirarch and bit selects.
2007-05-24 04:07:11 +00:00
steve
b981c81d37
Rework hname_t to use perm_strings.
2007-04-26 03:06:21 +00:00
steve
f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
steve
75ad90534b
Generalize signals to carry types.
2005-07-07 16:22:49 +00:00
steve
177b6ffb6a
Addtrbute keys are perm_strings.
2004-02-20 18:53:33 +00:00
steve
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
steve
46253ed873
Rework expression parsing and elaboration to
...
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
steve
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
steve
5eca5d9948
Carry integerness throughout the compilation.
2002-06-21 04:59:35 +00:00
steve
e6c0629626
Add language support for Verilog-2001 attribute
...
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
steve
ab6c8cb4b8
Parser and pform use hierarchical names as hname_t
...
objects instead of encoded strings.
2001-12-03 04:47:14 +00:00
steve
65020bc6de
Use the iosfwd header if available.
2001-01-16 02:44:17 +00:00
steve
5dbea64759
Add support for signed reg variables,
...
simulate in t-vvm signed comparisons.
2000-12-11 00:31:43 +00:00
steve
1db70a0c46
Move signal elaboration to a seperate pass.
2000-05-02 16:27:38 +00:00
steve
b734ecf02f
Macintosh compilers do not support ident.
2000-02-23 02:56:53 +00:00
steve
4cfa3e4047
Support the creation of scopes.
1999-11-27 19:07:57 +00:00
steve
37b60a4c52
Clean up interface of the PWire class,
...
Properly match wire ranges.
1999-06-17 05:34:42 +00:00
steve
f3a91a10b3
Line information with nets.
1999-06-02 15:38:46 +00:00
steve
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
steve
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
steve
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00