iverilog

Commit Graph

Author	SHA1	Message	Date
Martin Whitaker	6e5ed73b09	Extended fix for GitHub issue #99 . Most vvp functors need to support recv_vec4_pv. Any that are strength-aware also need to support recv_vec8_pv. Note the simplifying assumption that is documented in the base class recv_vec4_pv_ implementation.	2016-04-18 23:47:43 +01:00
Stephen Williams	d5fb0f4344	Handle some tricky conditions assignments to parts. When for example assigning to foo[<x>] within a contitional, and doing synthesis, we need to create a NetSubstitute device to manage the l-value bit selects.	2014-07-14 16:46:58 -07:00

Author

SHA1

Message

Date

Martin Whitaker

6e5ed73b09

Extended fix for GitHub issue #99 .

Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.

2016-04-18 23:47:43 +01:00

Stephen Williams

d5fb0f4344

Handle some tricky conditions assignments to parts.

When for example assigning to foo[<x>] within a contitional, and
doing synthesis, we need to create a NetSubstitute device to manage
the l-value bit selects.

2014-07-14 16:46:58 -07:00

2 Commits