This patch adds support for the various case statements and adds
preliminary support for instantiating modules. The module instantiation,
just like the module definition, is still missing ports. Adding this
will require modification to the compiler to get the port order correct.
Because of defparams and passed parameters any module that has a
parameter must be generated uniquely for each instance since they may not
all be the same. Modules without parameters are only generated once.
This patch adds the ability to print a delay expression (it is rescaled
to the module timescale) and adds support the following statement types:
nonblocking assignment with a delay (event control is still missing)
condition (if/else)
forever
repeat
while (Icarus translated for loops to while loops)
fork
procedural continuous assign
deassign
force
release
This patch adds support to the vlog95 convert for the ternary operator,
the concat/repeat operator and calling a system function. It also adds
the `celldefine information when appropriate.
This patch adds more support to the Verilog 1995 converter. There is
still a lot that is missing and there is still some implemented
functionality that is not 100%.
Cary R