luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
8,742 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

54 Commits

Author SHA1 Message Date
steve e5f5f41515 Elaborate gate ranges. 1999-02-15 02:06:15 +00:00
steve fb439c78b9 Add the LineInfo class to carry the source file 
location of things. PGate, Statement and PProcess.

 elaborate handles module parameter mismatches,
 missing or incorrect lvalues for procedural
 assignment, and errors are propogated to the
 top of the elaboration call tree.

 Attach line numbers to processes, gates and
 assignment statements.
 1999-01-25 05:45:56 +00:00
steve e097c999d5 Elaborate UDP devices, 
Support UDP type attributes, and
 pass those attributes to nodes that
 are instantiated by elaboration,
 Put modules into a map instead of
 a simple list.
 1998-12-01 00:42:13 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00