101b373293
Allow constant concat expressions.
2005-12-07 04:04:23 +00:00
8ed504b064
Fix for stubborn compiler.
2005-11-27 17:01:56 +00:00
908955c72c
Handle bit select of parameter with ranges.
2005-11-27 05:56:20 +00:00
c02b3b8ac6
Reorganize signal part select handling, and add support for
...
indexed part selects.
Expand expression constant propagation to eliminate extra
sums in certain cases.
2005-11-10 13:28:11 +00:00
a652719876
Add support for indexed select attached to parameters.
2005-10-04 04:09:25 +00:00
4a8be3db9c
Implement bi-directional part selects.
2005-08-06 17:58:16 +00:00
75ad90534b
Generalize signals to carry types.
2005-07-07 16:22:49 +00:00
9e94afe399
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 20:16:00 +00:00
8f2d679c8a
Unify elaboration of l-values for all proceedural assignments,
...
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
2004-12-29 23:55:43 +00:00
e4ae832153
Clean up spurious trailing white space.
2004-10-04 01:10:51 +00:00
e571dd90d8
Calculate delay statement delays using elaborated
...
expressions instead of pre-elaborated expression
trees.
Remove the eval_pexpr methods from PExpr.
2003-02-08 19:49:21 +00:00
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
cfd8cbf850
Port expressions for output ports are lnets, not nets.
2002-11-09 19:20:48 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
91a755d0e8
Add support for memory words in l-value of
...
blocking assignments, and remove the special
NetAssignMem class.
2002-06-04 05:38:43 +00:00
e6c0629626
Add language support for Verilog-2001 attribute
...
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
9ef49379f4
Add support for non-constant bit select.
2002-04-23 03:53:59 +00:00
5cf7355c91
Precalculate unary - if possible.
2002-04-14 03:55:25 +00:00
6733f7625b
Detect missing indices to memories (PR#421)
2002-04-13 02:33:17 +00:00
3d646aa92c
Constant expressions are not l-values for task ports.
2002-03-09 04:02:26 +00:00
b7c2bd4f72
Add the NetUserFunc netlist node.
2002-03-09 02:10:22 +00:00
03aebd7525
Support elaborate_net for PEString objects.
2001-12-30 21:32:03 +00:00
ab6c8cb4b8
Parser and pform use hierarchical names as hname_t
...
objects instead of encoded strings.
2001-12-03 04:47:14 +00:00
7793a49854
Remove string paths from PExpr elaboration.
2001-11-08 05:15:50 +00:00
6bfbcbdcf7
elaborate_lnet uses scope instead of string path.
2001-11-07 04:26:46 +00:00
bf72f39fe9
eval_const uses scope instead of a string path.
2001-11-07 04:01:59 +00:00
9572ddd7e8
Support more real arithmetic in delay constants.
2001-11-06 06:11:55 +00:00
219df169a3
Generalize the evaluation of floating point delays, and
...
get it working with delay assignment statements.
Allow parameters to be referenced by hierarchical name.
2001-01-14 23:04:55 +00:00
f4671a3082
Evaluate <= and ?: in parameter expressions (PR#81)
2000-12-16 19:03:30 +00:00
084a464cf1
Support decimal constants in behavioral delays.
2000-12-10 22:01:35 +00:00
f6507cba43
Check lvalue of procedural continuous assign (PR#29)
2000-12-06 06:31:09 +00:00
89d7176734
Add support for modulus (Eric Aardoom)
2000-09-17 21:26:15 +00:00
b6ce313e91
move lval elaboration to PExpr virtual methods.
2000-09-09 15:21:26 +00:00
d86b37d90f
Support unary + and - in constants.
2000-09-07 22:38:13 +00:00
056a3f7220
Allow unary operators in constant expressions.
2000-06-30 15:50:20 +00:00
80878e2e53
Support concatenation in parameter expressions.
2000-06-13 05:22:16 +00:00
9c1dc92d74
Parameters can be strings.
2000-06-01 02:31:39 +00:00
3676d66408
Module ports are really special PEIdent
...
expressions, because a name can be used
many places in the port list.
2000-05-16 04:05:15 +00:00
b90cda1f3f
Carry strength values from Verilog source to the
...
pform and netlist for gates.
Change vvm constants to use the driver_t to drive
a constant value. This works better if there are
multiple drivers on a signal.
2000-05-07 04:37:55 +00:00
fbe475ef7d
Add infrastructure for system functions, move
...
$time to that structure and add $random.
2000-05-04 03:37:58 +00:00
b1fd927acb
Named events really should be expressed with PEIdent
...
objects in the pform,
Handle named events within the mix of net events
and edges. As a unified lot they get caught together.
wait statements are broken into more complex statements
that include a conditional.
Do not generate NetPEvent or NetNEvent objects in
elaboration. NetEvent, NetEvWait and NetEvProbe
take over those functions in the netlist.
2000-04-12 04:23:57 +00:00
694ff934af
Add support for integer division.
2000-04-01 21:40:22 +00:00
2dd010dc04
Named events as far as the pform.
2000-04-01 19:31:57 +00:00
71a506a28a
Binary and unary operators in parameter expressions.
2000-03-12 18:22:11 +00:00
79f772200a
Allow parameter identifiers in parameter expressions.
2000-03-12 04:35:22 +00:00
e7efc2709a
Redesign the implementation of scopes and parameters.
...
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
2000-03-08 04:36:53 +00:00
b734ecf02f
Macintosh compilers do not support ident.
2000-02-23 02:56:53 +00:00
b354cf68b8
Fix up width matching in structural bitwise operators.
2000-02-16 03:58:27 +00:00
aa8908c52f
Multiplication all the way to simulation.
2000-01-13 03:35:35 +00:00
ced7cc6d60
Structural logical or.
1999-12-16 03:46:39 +00:00
a81dcd7955
Support memories in continuous assignments.
1999-11-21 00:13:08 +00:00
1624afe1ba
Add support for the LPM_CLSHIFT device.
1999-11-14 20:24:28 +00:00
206b37e5de
Fix NetConst being set to zero width, and clean
...
up elaborate_set_cmp_ for NetEBinary.
1999-11-05 21:45:19 +00:00
e1bbbe5614
Include subtraction in LPM_ADD_SUB device.
1999-10-31 20:08:24 +00:00
71ecf8c143
Add to netlist links pin name and instance number,
...
and arrange in vvm for pin connections by name
and instance number.
1999-10-31 04:11:27 +00:00
bb38653654
Parse system function calls.
1999-09-25 02:57:29 +00:00
31bdb87c8f
separate assign lval elaboration for error checking.
1999-09-15 04:17:52 +00:00
e69345b9fe
Elaborate and emit to vvm procedural functions.
1999-08-31 22:38:29 +00:00
dd8daf40df
elaborate rise/fall/decay for continuous assign.
1999-08-01 21:18:55 +00:00
e0a988bf7e
Add functions up to elaboration (Ed Carter)
1999-07-31 19:14:47 +00:00
9021f68996
is_constant method for PEConcat.
1999-07-22 02:05:20 +00:00
a5921ceae8
netlist support for ternary operator.
1999-07-17 19:50:59 +00:00
add2803267
More syntax parse with sorry stubs.
1999-06-16 03:13:29 +00:00
430d7b22e4
Add lexical support for real numbers.
1999-06-15 02:50:02 +00:00
7c2cf8b2fa
Add support for the Ternary operator,
...
Add support for repeat concatenation,
Correct some seg faults cause by elaboration
errors,
Parse the casex anc casez statements.
1999-06-10 04:03:52 +00:00
1464851e0e
Add support for procedural concatenation expression.
1999-06-09 03:00:05 +00:00
10ffaeda90
Redo constant expression detection to happen
...
after parsing.
Parse more operators and expressions.
1999-05-16 05:08:42 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
ce49708442
Parse OR of event expressions.
1999-04-29 02:16:26 +00:00
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
d27f260bc1
Check net ranges in declarations.
1998-11-11 00:01:51 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve