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Add support for $bits (SystemVerilog)

This commit is contained in:
steve 2002-05-24 00:44:54 +00:00
parent 7ce713356e
commit fde7cd8f10
2 changed files with 22 additions and 8 deletions
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16
README.txt
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@ -311,18 +311,23 @@ constructs.
- force to nets are not supported. Force to variables, and - force to nets are not supported. Force to variables, and
assign/deassign, are supported. assign/deassign, are supported.
5.1 Nonstandard Constructs 5.1 Nonstandard Constructs or Behaviors
Icarus Verilog includes some features that are not part of the Icarus Verilog includes some features that are not part of the
IEEE1364 standard, but have well defined meaning. These are extensions IEEE1364 standard, but have well defined meaning, and also sometimes
to the language. gives nonstandard (but extended) meanings to some features of the
language that are defined.
$sizeof(<expr>) $sizeof(<expr>)
This system function returns the size in bits of the $bits(<expr>)
The $bits system function returns the size in bits of the
expression that is its argument. The result of this expression that is its argument. The result of this
function is undefined if the argument doesn't have a function is undefined if the argument doesn't have a
self-determined size. self-determined size.
The $sizeof function is deprecated in favor of $bits, which is
the same thing, but included in the SystemVerilog definition.
Builtin system functions Builtin system functions
Certain of the system functions have well defined meanings, so Certain of the system functions have well defined meanings, so
@ -330,9 +335,10 @@ to the language.
using runtime VPI code. Doing so means that VPI cannot using runtime VPI code. Doing so means that VPI cannot
override the definitions of functions handled in this override the definitions of functions handled in this
manner. On the other hand, this makes them synthesizeable, and manner. On the other hand, this makes them synthesizeable, and
also allows for more agressive constant propagation. The also allows for more aggressive constant propagation. The
functions handled in this manner are: functions handled in this manner are:
$bits
$signed $signed
$sizeof $sizeof
$unsigned $unsigned

14
elab_expr.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elab_expr.cc,v 1.59 2002/05/06 02:30:27 steve Exp $" #ident "$Id: elab_expr.cc,v 1.60 2002/05/24 00:44:54 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -186,14 +186,19 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope) const
the bit width of the sub-expression. The value of the the bit width of the sub-expression. The value of the
sub-expression is not used, so the expression itself can be sub-expression is not used, so the expression itself can be
deleted. */ deleted. */
if (strcmp(path_.peek_name(0), "$sizeof") == 0) { if ((strcmp(path_.peek_name(0), "$sizeof") == 0)
|| (strcmp(path_.peek_name(0), "$bits") == 0)) {
if ((parms_.count() != 1) || (parms_[0] == 0)) { if ((parms_.count() != 1) || (parms_[0] == 0)) {
cerr << get_line() << ": error: The $sizeof() function " cerr << get_line() << ": error: The $bits() function "
<< "takes exactly one(1) argument." << endl; << "takes exactly one(1) argument." << endl;
des->errors += 1; des->errors += 1;
return 0; return 0;
} }
if (strcmp(path_.peek_name(0), "$sizeof") == 0)
cerr << get_line() << ": warning: $sizeof is deprecated."
<< " Use $bits() instead." << endl;
PExpr*expr = parms_[0]; PExpr*expr = parms_[0];
NetExpr*sub = expr->elaborate_expr(des, scope, true); NetExpr*sub = expr->elaborate_expr(des, scope, true);
verinum val (sub->expr_width(), sizeof(unsigned)); verinum val (sub->expr_width(), sizeof(unsigned));
@ -864,6 +869,9 @@ NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
/* /*
* $Log: elab_expr.cc,v $ * $Log: elab_expr.cc,v $
* Revision 1.60 2002/05/24 00:44:54 steve
* Add support for $bits (SystemVerilog)
*
* Revision 1.59 2002/05/06 02:30:27 steve * Revision 1.59 2002/05/06 02:30:27 steve
* Allow parameters in concatenation of widths are defined. * Allow parameters in concatenation of widths are defined.
* *