Rework handling of timescales in parser.

This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.

Module.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2016 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2017 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -35,7 +35,6 @@ Module::Module(LexicalScope*parent, perm_string n)
       is_interface = false;
       program_block = false;
       uc_drive = UCD_NONE;
-      timescale_warn_done = false;
 }
 
 Module::~Module()