Be more precide about mappings to Verilog types.

Make std_logic map to Verilog logic, and integers and bits map
to Verilog bool. These are more precise and accurate.

vhdlpp/entity.h

@@ -75,8 +75,9 @@ class Entity : public LineInfo {
       std::map<perm_string,Architecture*>arch_;
       Architecture*bind_arch_;
 
-      enum vtype_t { VNONE, VUWIRE };
+      enum vtype_t { VNONE, VBOOL, VLOGIC };
       struct decl_t {
+	    bool signed_flag;
 	    vtype_t type;
 	    long msb, lsb;
       };

vhdlpp/entity_elaborate.cc

@@ -87,17 +87,24 @@ int Entity::elaborate_ports_(void)
 	    InterfacePort*cur_port = *cur;
 	    decl_t cur_decl;
 	    cur_decl.type = VNONE;
+	    cur_decl.signed_flag = false;
 	    cur_decl.msb = 0;
 	    cur_decl.lsb = 0;
 
 	    if (strcasecmp(cur_port->type_name, "std_logic") == 0) {
-		  cur_decl.type = VUWIRE;
+		  cur_decl.type = VLOGIC;
 
 	    } else if (strcasecmp(cur_port->type_name, "bit") == 0) {
-		  cur_decl.type = VUWIRE;
+		  cur_decl.type = VBOOL;
 
 	    } else if (strcasecmp(cur_port->type_name, "boolean") == 0) {
-		  cur_decl.type = VUWIRE;
+		  cur_decl.type = VBOOL;
+
+	    } else if (strcasecmp(cur_port->type_name, "integer") == 0) {
+		  cur_decl.type = VBOOL;
+		  cur_decl.signed_flag = true;
+		  cur_decl.msb = 31;
+		  cur_decl.lsb = 0;
 
 	    } else {
 		  cerr << get_fileline() << ": error: "

vhdlpp/entity_emit.cc

@@ -49,6 +49,8 @@ int Entity::emit(ostream&out)
 		       ; cur != ports_.end() ; ++cur) {
 		  InterfacePort*port = *cur;
 
+		  decl_t&decl = declarations_[port->name];
+
 		  if (sep) out << sep;
 		  else sep = ", ";
 
@@ -57,10 +59,18 @@ int Entity::emit(ostream&out)
 			out << "NO_PORT " << port->name;
 			break;
 		      case PORT_IN:
-			out << "input " << port->name;
+			out << "input ";
+			if (decl.msb != decl.lsb)
+			      out << "[" << decl.msb
+				  << ":" << decl.lsb << "] ";
+			out << port->name;
 			break;
 		      case PORT_OUT:
-			out << "output " << port->name;
+			out << "output ";
+			if (decl.msb != decl.lsb)
+			      out << "[" << decl.msb
+				  << ":" << decl.lsb << "] ";
+			out << port->name;
 			break;
 		  }
 	    }
@@ -76,8 +86,16 @@ int Entity::emit(ostream&out)
 		case VNONE:
 		  out << "// N type for " << cur->first << endl;
 		  break;
-		case VUWIRE:
+		case VLOGIC:
-		  out << "wire ";
+		  out << "wire logic ";
+		  if (cur->second.msb != cur->second.lsb)
+			out << "[" << cur->second.msb
+			    << ":" << cur->second.lsb << "] ";
+		  out << cur->first << ";" << endl;
+		case VBOOL:
+		  out << "wire bool ";
+		  if (cur->second.signed_flag)
+			out << "signed ";
 		  if (cur->second.msb != cur->second.lsb)
 			out << "[" << cur->second.msb
 			    << ":" << cur->second.lsb << "] ";