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parser: Require SystemVerilog for implicit named port connections 

Implicit named port connections are only supported by SystemVerilog. Add a
check to generate an error when trying to use it in Verilog mode.

Regression test br_gh315 is modified to run in SystemVerilog mode since it
makes use of implicit named port connections.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2023-06-12 20:31:11 -07:00
parent d040804036
commit ee4476fed2
2 changed files with 3 additions and 2 deletions
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2
ivtest/regress-vlg.list
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@ -325,7 +325,7 @@ br_gh283a normal ivltests
br_gh283b normal ivltests
br_gh283c normal ivltests
br_gh309 normal ivltests
br_gh315 normal,-gspecify ivltests
br_gh315 normal,-g2005-sv,-gspecify ivltests
br_gh316a normal,-gspecify ivltests
br_gh316b normal,-gspecify ivltests
br_gh316c normal,-gspecify ivltests

3
parse.y
View File

@ -5728,7 +5728,8 @@ port_name
$$ = tmp;
}
| attribute_list_opt '.' IDENTIFIER
{ named_pexpr_t*tmp = new named_pexpr_t;
{ pform_requires_sv(@3, "Implicit named port connections");
named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make($3);
tmp->parm = new PEIdent(lex_strings.make($3), true);
FILE_NAME(tmp->parm, @3);