From ee4476fed2ada40b6c3572c3da667a1b8ce2bcd9 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 12 Jun 2023 20:31:11 -0700 Subject: [PATCH] parser: Require SystemVerilog for implicit named port connections Implicit named port connections are only supported by SystemVerilog. Add a check to generate an error when trying to use it in Verilog mode. Regression test br_gh315 is modified to run in SystemVerilog mode since it makes use of implicit named port connections. Signed-off-by: Lars-Peter Clausen --- ivtest/regress-vlg.list | 2 +- parse.y | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 862fcbc63..858dc4bc9 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -325,7 +325,7 @@ br_gh283a normal ivltests br_gh283b normal ivltests br_gh283c normal ivltests br_gh309 normal ivltests -br_gh315 normal,-gspecify ivltests +br_gh315 normal,-g2005-sv,-gspecify ivltests br_gh316a normal,-gspecify ivltests br_gh316b normal,-gspecify ivltests br_gh316c normal,-gspecify ivltests diff --git a/parse.y b/parse.y index 8c548476c..5c98f4fb1 100644 --- a/parse.y +++ b/parse.y @@ -5728,7 +5728,8 @@ port_name $$ = tmp; } | attribute_list_opt '.' IDENTIFIER - { named_pexpr_t*tmp = new named_pexpr_t; + { pform_requires_sv(@3, "Implicit named port connections"); + named_pexpr_t*tmp = new named_pexpr_t; tmp->name = lex_strings.make($3); tmp->parm = new PEIdent(lex_strings.make($3), true); FILE_NAME(tmp->parm, @3);