luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vhdlpp: Evaluate conditional signal assignments upon simulation start.

This commit is contained in:
Maciej Suminski 2016-06-15 17:19:27 +02:00
parent 798adc9863
commit ed3e67926f
1 changed files with 16 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
vhdlpp/architec_emit.cc
View File

@ -152,22 +152,9 @@ int CondSignalAssignment::emit(ostream&out, Entity*ent, Architecture*arc)
int errors = 0; int errors = 0;
out << "// " << get_fileline() << endl; out << "// " << get_fileline() << endl;
out << "always @("; out << "always begin" << endl;
bool first = true; bool first = true;
for(list<const ExpName*>::const_iterator it = sens_list_.begin();
it != sens_list_.end(); ++it) {
if(first)
first = false;
else
out << ",";
errors += (*it)->emit(out, ent, arc);
}
out << ") begin" << endl;
first = true;
for(list<ExpConditional::case_t*>::iterator it = options_.begin(); for(list<ExpConditional::case_t*>::iterator it = options_.begin();
it != options_.end(); ++it) { it != options_.end(); ++it) {
ExpConditional::case_t*cas = *it; ExpConditional::case_t*cas = *it;
@ -192,6 +179,21 @@ int CondSignalAssignment::emit(ostream&out, Entity*ent, Architecture*arc)
out << ";" << endl; out << ";" << endl;
} }
// Sensitivity list
first = true;
out << "@(";
for(list<const ExpName*>::const_iterator it = sens_list_.begin();
it != sens_list_.end(); ++it) {
if(first)
first = false;
else
out << ",";
errors += (*it)->emit(out, ent, arc);
}
out << ");" << endl;
out << "end" << endl; out << "end" << endl;
return errors; return errors;