VHDL: make casez support 'x' and handle a full don't care case.
The VHDL converter erroneously treated a casez and casex exactly the same. In reality a casez compares a 'x' value (it is not a don't care). It also adds support for a full don't care case by just returning True for the condition.
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@ -608,30 +608,36 @@ int draw_casezx(vhdl_procedural *proc, stmt_container *container,
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vhdl_binop_expr *all =
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vhdl_binop_expr *all =
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new vhdl_binop_expr(VHDL_BINOP_AND, vhdl_type::boolean());
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new vhdl_binop_expr(VHDL_BINOP_AND, vhdl_type::boolean());
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bool just_dont_care = true;
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for (unsigned i = 0; i < ivl_expr_width(net); i++) {
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for (unsigned i = 0; i < ivl_expr_width(net); i++) {
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switch (bits[i]) {
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switch (bits[i]) {
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case 'x':
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if (ivl_statement_type(stmt) == IVL_ST_CASEZ) break;
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case '?':
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case '?':
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case 'z':
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case 'z':
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case 'x':
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// Ignore it
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// Ignore it
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break;
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continue;
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default:
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{
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// Generate a comparison for this bit position
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vhdl_binop_expr *cmp =
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new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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vhdl_type *type = vhdl_type::nunsigned(ivl_expr_width(net));
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vhdl_var_ref *lhs =
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new vhdl_var_ref(test->get_name().c_str(), type);
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lhs->set_slice(new vhdl_const_int(i));
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cmp->add_expr(lhs);
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cmp->add_expr(new vhdl_const_bit(bits[i]));
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all->add_expr(cmp);
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}
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}
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}
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// Generate a comparison for this bit position
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vhdl_binop_expr *cmp =
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new vhdl_binop_expr(VHDL_BINOP_EQ, vhdl_type::boolean());
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vhdl_type *type = vhdl_type::nunsigned(ivl_expr_width(net));
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vhdl_var_ref *lhs =
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new vhdl_var_ref(test->get_name().c_str(), type);
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lhs->set_slice(new vhdl_const_int(i));
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cmp->add_expr(lhs);
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cmp->add_expr(new vhdl_const_bit(bits[i]));
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all->add_expr(cmp);
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just_dont_care = false;
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}
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// If there are no bits comparisons then just put a True
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if (just_dont_care) {
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all->add_expr(new vhdl_const_bool(true));
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}
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}
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if (result)
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if (result)
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