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Real multiply in a cont. assign. is always 1 bit wide. 

The continuous assignment multiply expands vectors to the sum
of the two widths. This is correct for bit based vectors, but
for real variables it should always be one bit wide.
This commit is contained in:
Cary R 2008-01-16 19:26:25 -08:00 committed by Stephen Williams
parent d992ec4bd4
commit ea1f448300
1 changed files with 9 additions and 3 deletions
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12
elab_net.cc
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@ -1011,7 +1011,7 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
// The mult is signed if both its operands are signed.
bool arith_is_signed = lsig->get_signed() && rsig->get_signed();
/* The arguments of a divide must have the same type. */
/* The arguments of a multiply must have the same type. */
if (lsig->data_type() != rsig->data_type()) {
cerr << get_fileline() << ": error: Arguments of multiply "
<< "have different data types." << endl;
@ -1025,8 +1025,14 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
unsigned rwidth = lwidth;
if (rwidth == 0) {
rwidth = lsig->vector_width() + rsig->vector_width();
lwidth = rwidth;
/* Reals are always 1 wide and lsig/rsig types match here. */
if (lsig->data_type() == IVL_VT_REAL) {
rwidth = 1;
lwidth = 1;
} else {
rwidth = lsig->vector_width() + rsig->vector_width();
lwidth = rwidth;
}
}
if (arith_is_signed) {