From ea1f448300153650997acb7837f70fade191e6bf Mon Sep 17 00:00:00 2001 From: Cary R Date: Wed, 16 Jan 2008 19:26:25 -0800 Subject: [PATCH] Real multiply in a cont. assign. is always 1 bit wide. The continuous assignment multiply expands vectors to the sum of the two widths. This is correct for bit based vectors, but for real variables it should always be one bit wide. --- elab_net.cc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/elab_net.cc b/elab_net.cc index 35d98c25d..9041e1dac 100644 --- a/elab_net.cc +++ b/elab_net.cc @@ -1011,7 +1011,7 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope, // The mult is signed if both its operands are signed. bool arith_is_signed = lsig->get_signed() && rsig->get_signed(); - /* The arguments of a divide must have the same type. */ + /* The arguments of a multiply must have the same type. */ if (lsig->data_type() != rsig->data_type()) { cerr << get_fileline() << ": error: Arguments of multiply " << "have different data types." << endl; @@ -1025,8 +1025,14 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope, unsigned rwidth = lwidth; if (rwidth == 0) { - rwidth = lsig->vector_width() + rsig->vector_width(); - lwidth = rwidth; + /* Reals are always 1 wide and lsig/rsig types match here. */ + if (lsig->data_type() == IVL_VT_REAL) { + rwidth = 1; + lwidth = 1; + } else { + rwidth = lsig->vector_width() + rsig->vector_width(); + lwidth = rwidth; + } } if (arith_is_signed) {