luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Handle signed IVL_VT_BOOL load into integer. 

The %ix/get should be %is/get/s if the source expression is
signed. This gets proper sign extension.
This commit is contained in:
Stephen Williams 2010-10-21 17:04:56 -07:00
parent 9037354c6b
commit e5597d5f44
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tgt-vvp/eval_bool.c
View File

@ -47,10 +47,14 @@ static int eval_bool64_logic(ivl_expr_t expr)
{ {
int res; int res;
struct vector_info tmp; struct vector_info tmp;
const char*s_flag = "";
tmp = draw_eval_expr(expr, STUFF_OK_XZ); tmp = draw_eval_expr(expr, STUFF_OK_XZ);
res = allocate_word(); res = allocate_word();
fprintf(vvp_out, " %%ix/get %d, %u, %u;\n", res, tmp.base, tmp.wid); if (ivl_expr_signed(expr))
s_flag = "/s";
fprintf(vvp_out, " %%ix/get%s %d, %u, %u;\n", s_flag, res, tmp.base, tmp.wid);
clr_vector(tmp); clr_vector(tmp);
return res; return res;