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Merge branch 'master' of github.com:steveicarus/iverilog

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Stephen Williams
2012-01-10 18:23:33 -08:00
parent 6662a3f78a ea065a674d
commit e1c0fa5feb
1 changed files with 1 additions and 1 deletions
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parse.y
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@@ -3041,7 +3041,7 @@ module_item
current_function = 0; current_function = 0;
delete[]$4; delete[]$4;
if ($7==0 && !gn_system_verilog()) { if ($7==0 && !gn_system_verilog()) {
yyerror(@7, "error: Empty parenthesis syntax requires SystemVerilog."); yyerror(@4, "error: Empty parenthesis syntax requires SystemVerilog.");
} }
} }
| K_function automatic_opt function_range_or_type_opt IDENTIFIER error K_endfunction | K_function automatic_opt function_range_or_type_opt IDENTIFIER error K_endfunction